Pattern pre-processing apparatus

Claim 2

In a pattern recognition system, a pattern pre-processing apparatus for modifying a quantized input pattern obtained by the scanning of a pattern, by the conversion into a first digital value of a signal produced in the case of said scanning of a pattern area, and by the conversion into a second digital value of a signal produced in the case of said scanning of a background area, said pattern pre-processing apparatus comprising: at least one shift register for storing and shifting therein said input pattern in the order in which it has been scanned, and pattern thinning means for receiving, on the basis of a first prespecified bit position of said shift register, the bit contents in accordance with said input pattern of said shift register corresponding to selected bit positions located adjacent to said first prespecified bit position, including means for producing a signal of said second digital value when the contents of said adjoining bit positions indicate any one of predetermined patterns, and for producing a signal indicating as before the content of said first prespecified bit position when the contents of said adjoining bit positions indicate none of said predetermined patterns, said pattern thinning means including a plurality of circuit means for examining whether said contents of said adjoining bit positions indicate any one of said predetermined patterns, said circuit means producing a signal of said second digital value as an output of said pattern pre-processing apparatus when the content of a peripheral portion of said pattern area is shifted to said first prespecified bit position, thereby leaving only a skeletal portion of said pattern area in the state of said first digital value.

Claim 3

A pattern pre-processing apparatus according to claim 1, further including gap filling means for receiving, on the basis of a second prespecified bit position of said shift register located in the rear of said first prespecified bit position in the shifting direction, the bit contents in accordance with the input pattern of thE shift register corresponding to selected bit positions located adjacent to said second prespecified bit position and converting the content of said second prespecified bit position into said first digital value when said selected bit positions located adjacent to said second prespecified bit position indicate a predetermined condition.

Claim 4

A pattern pre-processing apparatus according to claim 1, further including detecting means, said detecting means producing a signal indicative of the beginning of the input pattern when the content of a third prespecified bit position of the shift register and the bit contents in accordance with the input pattern of the shift register corresponding to selected bit positions located adjacent to said third prespecified bit position indicate a predetermined condition, said detecting means producing a signal indicative of the end of the input pattern when said first digital value has not been shifted to a fourth prespecified bit position of the shift register during a predetermined number of scanning.

Claim 5

A pattern pre-processing apparatus according to claim 2, further including detecting means, said detecting means producing a signal indicative of the beginning of the input pattern when the content of a third prespecified bit position and the bit contents in accordance with the input pattern of the shift register corresponding to selected bit positions located adjacent to said third prespecified bit position indicate a predetermined condition, said detecting producing a signal indicative of the end of the input pattern when said first digital value has not been shifted to a fourth prespecified bit position of the shift register during a predetermined number of scanning.

Claim 6

A pattern pre-processing apparatus according to claim 1, wherein said pattern thinning means comprise a plurality of AND logic means each producing a signal when, on the basis of the first prespecified bit position of the shift register, the bit contents in accordance with the input pattern of the shift register corresponding to selected bit positions located adjacent to the first prespecified bit position indicate associated one of the predetermined patterns, and output means for producing a signal of said first digital value when at least one of said plurality of AND logic means produces a signal, and for producing a signal indicating as before the content of the first prespecified bit position when none of said plurality of AND logic means produces a signal.

Claim 7

In a pattern recognition system, a pattern pre-processing apparatus for modifying a quantized input pattern obtained by the scanning of a pattern, by the conversion into a first digital value of a signal produced in the case of the scanning of a pattern area, and by the conversion into a second digital value of a signal produced in the case of the scanning of a background area, said pattern pre-processing apparatus comprising: a first shift register for storing and shifting said input pattern in the order in which said input pattern has been scanned; gap filling means for receiving, on the basis of a second prespecified bit position of said first shift register, the bit contents in accordance with said input pattern of said first shift register corresponding to selected bit positions located adjacent to said second prespecified bit position and putting the content of said second prespecified bit position into the first digital value when the contents of said adjacent bit positions indicate a predetermined condition; first pattern thinning means for receiving, on the basis of a first prespecified bit position of said first shift register, the bit contents in accordance with said input pattern of said first shift register corresponding to selected bit positions located adjacent to said first prespecified bit position for producing a signal of the second digital value when the contents of said bit positions located adjacent to said first prespecified bit position indicate any one of prEdetermined patterns, and for producing a signal indicating as before the content of said first prespecified bit position when the contents of said bit positions located adjacent to said first prespecified bit position indicate none of said predetermined patterns, thereby converting the first digital value of said first prespecified bit position into the second digital value when a signal obtained from a peripheral portion of said pattern area is shifted to said first prespecified bit position of said shift register; a second shift register for sequentially receiving the output signals from said first pattern thinning means to store and shift therein; detecting means for producing a signal indicative of the beginning of said input pattern when the content of a third prespecified bit position in said second shift register and the bit contents in accordance with said input pattern of said second shift register corresponding to selected bit positions located adjacent to said third prespecified bit position indicate any one of the predetermined set of conditions, said detecting means producing a signal indicative of the end of said input pattern when the first digital value has not been shifted to a fourth bit position in said second shift register during a predetermined number of scanning; second pattern thinning means for receiving, on the basis of a fifth prespecified bit position in said second shift register, the bit contents in accordance with said input pattern of said second shift register corresponding to selected bit positions located adjacent to said fifth prespecified bit position for producing a signal of the second digital value when the contents of said selected bit positions located adjacent to said fifth prespecified bit position indicate any one of the predetermined patterns, and for producing a signal indicating as before the content of said fifth prespecified bit position when the contents of said bit positions located adjacent to said fifth prespecified bit position indicate none of said predetermined patterns, thereby converting the first digital value of said fifth prespecified bit position into the second digital value when a signal obtained from a peripheral portion of a pattern area which is thinned by said first pattern thinning means is shifted to said fifth prespecified bit position of said second shift register; a third shift register for sequentially receiving the output signals from said second pattern thinning means to store and shift therein; and third pattern thinning means for receiving, on the basis of a sixth prespecified bit position in said third shift register, the bit contents in accordance with said input pattern of said third shift register corresponding to selected bit positions located adjacent to said sixth bit position for producing a signal of the second digital value when the contents of said selected bit positions located adjacent to said sixth bit position indicate any one of the predetermined patterns, and for producing a signal indicating as before the content of said sixth prespecified bit position when the contents of said bit positions located adjacent to said sixth prespecified bit position indicate none of the predetermined patterns, thereby leaving a skeletal portion of said input pattern in the state of the first digital value.

Claim 8

In a pattern recognition system, a pattern pre-processing apparatus for modifying a quantized input pattern obtained by the scanning of a pattern, by the conversion into a first digital value of a signal produced in the case of the scanning of a pattern area, and by the conversion into a second digital value of a signal produced in the case of the scanning of a background area, said pattern pre-processing apparatus comprising: a first shift register for storing and shifting said input pattern in the order in which said input pattern has been scanned; gap filling means for receiving, on the basis of a second prespecified bit position of said first shift register, the bit contents in accordance with said input pattern of said first shift register corresponding to selected bit positions located adjacent to said second prespecified bit position and putting the content of said second prespecified bit position into the first digital value when the contents of said adjacent bit positions indicate a predetermined condition; first pattern thinning means for receiving, on the basis of a first prespecified bit position of said first shift register, the bit contents in accordance with said input pattern of said first shift register corresponding to selected bit positions located adjacent to said first prespecified bit position for producing a signal of the second digital value when the contents of said bit positions located adjacent to said first prespecified bit position indicate any one of prEdetermined patterns, and for producing a signal indicating as before the content of said first prespecified bit position when the contents of said bit positions located adjacent to said first prespecified bit position indicate none of said predetermined patterns, thereby converting the first digital value of said first prespecified bit position into the second digital value when a signal obtained from a peripheral portion of said pattern area is shifted to said first prespecified bit position of said shift register; a second shift register for sequentially receiving the output signals from said first pattern thinning means to store and shift therein; detecting means for producing a signal indicative of the beginning of said input pattern when the content of a third prespecified bit position in said second shift register and the bit contents in accordance with said input pattern of said second shift register corresponding to selected bit positions located adjacent to said third prespecified bit position indicate any one of the predetermined set of conditions, said detecting means producing a signal indicative of the end of said input pattern when the first digital value has not been shifted to a fourth bit position in said second shift register during a predetermined number of scanning; second pattern thinning means for receiving, on the basis of a fifth prespecified bit position in said second shift register, the bit contents in accordance with said input pattern of said second shift register corresponding to selected bit positions located adjacent to said fifth prespecified bit position for producing a signal of the second digital value when the contents of said selected bit positions located adjacent to said fifth prespecified bit position indicate any one of the predetermined patterns, and for producing a signal indicating as before the content of said fifth prespecified bit position when the contents of said bit positions located adjacent to said fifth prespecified bit position indicate none of said predetermined patterns, thereby converting the first digital value of said fifth prespecified bit position into the second digital value when a signal obtained from a peripheral portion of a pattern area which is thinned by said first pattern thinning means is shifted to said fifth prespecified bit position of said second shift register; a third shift register for sequentially receiving the output signals from said second pattern thinning means to store and shift therein; and third pattern thinning means for receiving, on the basis of a sixth prespecified bit position in said third shift register, the bit contents in accordance with said input pattern of said third shift register corresponding to selected bit positions located adjacent to said sixth bit position for producing a signal of the second digital value when the contents of said selected bit positions located adjacent to said sixth bit position indicate any one of the predetermined patterns, and for producing a signal indicating as before the content of said sixth prespecified bit position when the contents of said bit positions located adjacent to said sixth prespecified bit position indicate none of the predetermined patterns, thereby leaving a skeletal portion of said input pattern in the state of the first digital value.