US3855593A
Expired / Lapsed
US
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Pulse radar apparatus
Assignee: Thales Nederland BV
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Filing: 1973-04-17
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Granted: 1974-12-17
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Expires: 1993-04-17
Abstract
Abstract Pulse radar apparatus capable to generate cyclically a train of transmitter pulses with interpulse periods T1, T2, T1 + Delta T and T2 + Delta T. This apparatus comprises successively a receiver, a digital double canceller with a periodic shift time equalling the smallest interpulse period, a digital-to-analogue converter, a standard-pulse generator, a digital delay-line integrator with said periodic shift time, two parallel-connected branches meeting at a gate circuit, one branch comprising, successively, a first comparator and a correlator, and the other branch a second comparator and a delay element with a delay time of Delta T. The threshold level of the first comparator is maximally equal to that of the second comparator. On the receipt of each two sequential video signals with an interval Delta T the correlator causes that the gate circuit blocks the access to a PPI for the corresponding video signals supplied via the delay element.
Inventors
- 👤 Hijfte H Van
- 👤 J Ehbel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 16:18
CPC Classifications
G; G01; G01S; G01S13/00; G01S13/02; G01S13/50; G01S13/52; G01S13/522; G01S13/524; G01S13/526; G01S13/528; G01S13/06; G01S13/08; G01S13/10; G01S13/22; G01S13/225
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
264 words
Pulse radar apparatus comprising a transmitter capable to generate a train of transmitter pulses with at least a double stagger of interpulse periods, a receiver, and means with the aid of which video signals of multiple-time-around target echoes are eliminated from a plan position indicator (PPI), wherein said means comprise at least a (first) combination of a quantizer and a digital memory, and also an elimination circuit, the digital memory containing at least one active memory part and a combination circuit, which is fed, directly as well as via said memory part, with the sequential video signals supplied via the quantizer, whereby the memory part is operative only for a fixed duration, which starts from the moment a transmitter pulse is generated and which is maximally equal to the smallest interpulse period employed, and which memory part imposes upon each quantized video signal supplied, in addition to a delay corresponding with said first duration, a delay which is due to an inoperative state of said memory part, said state occurring during said fixed duration, and whereby the elimination circuit is provided with a delay element, a correlator and a gate circuit, where the video signals, being fed from the digital memory to the elimination circuit, are applied to the delay element and also to the correlator which, on the receipt of each two video signals succeeding each other with an interval equal to the smallest possible time difference between the interpulse periods employed, causes that the gate circuit blocks the access to the PPI for the corresponding video signals supplied via the delay element.
Claim 2
Dependent Claim
264 words
Pulse radar apparatus comprising a transmitter capable to generate a train of transmitter pulses with at least a double stagger of interpulse periods, a receiver, and means with the aid of which video signals of multiple-time-around target echoes are eliminated from a plan position indicator (PPI), wherein said means comprise at least a (first) combination of a quantizer and a digital memory, and also an elimination circuit, the digital memory containing at least one active memory part and a combination circuit, which is fed, directly as well as via said memory part, with the sequential video signals supplied via the quantizer, whereby the memory part is operative only for a fixed duration, which starts from the moment a transmitter pulse is generated and which is maximally equal to the smallest interpulse period employed, and which memory part imposes upon each quantized video signal supplied, in addition to a delay corresponding with said first duration, a delay which is due to an inoperative state of said memory part, said state occurring during said fixed duration, and whereby the elimination circuit is provided with a delay element, a correlator and a gate circuit, where the video signals, being fed from the digital memory to the elimination circuit, are applied to the delay element and also to the correlator which, on the receipt of each two video signals succeeding each other with an interval equal to the smallest possible time difference between the interpulse periods employed, causes that the gate circuit blocks the access to the PPI for the corresponding video signals supplied via the delay element.
Claim 3
Dependent Claim
68 words
Pulse radar apparatus as claimed in claim 1, wherein the correlator is provided with two series-connected delay elements, each of which having a delay time equal to the smallest possible time difference between the interpulse periods being employed, whereby each of said delay elements is bridged by an AND gate, and whereby the output signals of said AND gates control said gate circuit via a common OR gate.
Claim 4
Dependent Claim
148 words
Pulse radar apparatus as claimed in claim 1 wherein the digital memory is designed as a delay line integrator, which comprises a number of series-connected active memory parts of the kind already set forth and wherein two comparators are provided between the digital memory and the elimination circuit, whereby said correlator and said delay element are connected separately to said comparators, the comparator connected to the correlator having a threshold level that is maximally equal to the threshold level of the comparator connected to the delay element, and whereby the quantizer generates a standardized video pulse for each applied video signal exceeding a certain theshold level, which standardized video pulse is fed, directly as well as with a delay imposed by at least one of the memory parts of the delay-line integrator, to the corresponding combination circuit, the output signal of which being applied to the two comparators.
Claim 5
Dependent Claim
66 words
Pulse radar apparatus as claimed in claim 1, wherein a second combination of an additional quantizer and an additional digital memory is provided between the receiver and said first combination, whereby the additional quantizer is designed as an analogue-to-digital converter and the additional digital memory as a double canceller, and wherein the first combination is connected to the second combination by means of a digital-to-analogue converter.
Claim 6
Dependent Claim
49 words
Pulse radar apparatus as claimed in claim 1, whereby the transmitter is capable to generate a train of transmitter pulses with an even number of staggered interpulse periods, said interpulse periods being grouped in pairs such that between each two periods thus grouped and smallest time difference is obtained.
Claim 7
Dependent Claim
45 words
Pulse radar apparatus as claimed in claim 5, whereby the transmitter is capable to generate a train of transmitter pulses with four-stagger interpulse periods, each three sequential interpulse periods containing two grouped interpulse periods between which an interpulse period of the other pair is situated.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-12-16 | 1978-06-17 | 1978-12-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-12-16 | 1982-06-17 | 1982-12-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-12-16 | 1986-06-17 | 1986-12-17 | $7700.00 | Window Closed / Lapsed |