Patent US3940566A successfully refreshed from Google Patents.
US3940566A
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Arrangement for preventing interruptions in a time division multiplex transmission link for transfer of data
Assignee: Telefonaktiebolaget LM Ericsson AB
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Filing: 1974-09-12
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Granted: 1976-02-24
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Expires: 1994-09-12
Abstract
Abstract The present invention relates to an arrangement in a time division multiplex link having at least two pairs of multiplexors and demultiplexors interconnected by separate transmission lines, i.e., redundant transmission systems, with delay, in which time division multiplex channels are formed through the cyclic scanning of the multiplexor inlets and demultiplexor outlets, respectively so that data signals presented to the multiplexor inlets are transferred via the time division multiplex channels in the form of sampling signals to regeneration arrangements connected to the demultiplexor outlets. The sampling signals passed over the separated (redundant) time division multiplex channels are interlaced, i.e., different delays on different transmission lines, thereby producing a resultant sampling density which, when a fault occurs, is reduced by a factor corresponding to the share of the faulty channel in the total number of channels.
Inventors
- 👤 Martin Wilhelm Ivan Jeppsson
- 👤 Bruce William Lindstrom
- 👤 David John Russell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 23:36
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/04; H04B; H04B1/00; H04B1/74
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
279 words
In a time division multiplex transmission link for the transfer of binary data from a number of inlets to a corresponding number of outlets, the combination comprising a first multiplexor, a first transmission line and a first multiplexor connecting the inlets to the outlets, a second multiplexor, a second transmission line and a second demultiplexor also connecting the inlets to the outlets, each of said multiplexors generating sampling values resulting from the cyclical scanning of the inlets in response to the receipt of first addressing signals wherein each addressing signal is associated with one of the inlets, each sampling value representing the instantaneous value of the data when an inlet is scanned, means for transferring the sampling values from said multiplexors via the associated transmission line to the associated demultiplexor, means in the demultiplexors for transferring the received sampling values to the outlets in response to the receipt of second addressing signals, wherein each second addressing signal is associated with one of the outlets, a first addressing means for sequentially generating a first set of said first addressing signals for transfer to said first multiplexor, a second addressing means for sequentially generating a second set of said first addressing signals for transfer to said second multiplexor, said first and second sets being interleaved in time, a third addressing means for sequentially generating a first set of said second addressing signals for transfer to said first demultiplexor, a fourth addressing means for sequentially generating a second set of said second addressing signals for transfer to said second demultiplexor, said first and second sets of said second addressing signals being interleaved in time, and synchronizing means for intersynchronizing said addressing means.
Claim 2
Dependent Claim
279 words
In a time division multiplex transmission link for the transfer of binary data from a number of inlets to a corresponding number of outlets, the combination comprising a first multiplexor, a first transmission line and a first multiplexor connecting the inlets to the outlets, a second multiplexor, a second transmission line and a second demultiplexor also connecting the inlets to the outlets, each of said multiplexors generating sampling values resulting from the cyclical scanning of the inlets in response to the receipt of first addressing signals wherein each addressing signal is associated with one of the inlets, each sampling value representing the instantaneous value of the data when an inlet is scanned, means for transferring the sampling values from said multiplexors via the associated transmission line to the associated demultiplexor, means in the demultiplexors for transferring the received sampling values to the outlets in response to the receipt of second addressing signals, wherein each second addressing signal is associated with one of the outlets, a first addressing means for sequentially generating a first set of said first addressing signals for transfer to said first multiplexor, a second addressing means for sequentially generating a second set of said first addressing signals for transfer to said second multiplexor, said first and second sets being interleaved in time, a third addressing means for sequentially generating a first set of said second addressing signals for transfer to said first demultiplexor, a fourth addressing means for sequentially generating a second set of said second addressing signals for transfer to said second demultiplexor, said first and second sets of said second addressing signals being interleaved in time, and synchronizing means for intersynchronizing said addressing means.
Claim 3
Dependent Claim
79 words
The combination of claim 1 wherein each of said addressing means comprises an address memory with a number of memory cells, a write-in arrangement including means for writing into said memory cells scanning addresses in correspondence to the inlets or outlets, and a read-out arrrangement including means for cyclically scanning said memory cells at a rate at which said sampling values are to be transferred to said transmission lines and means for converting the addresses to the addressing signals.
Claim 4
Dependent Claim
23 words
The combination of claim 2 wherein the memory cells of address memories are sequentially scanned in sychronism in response to said synchronizing means.
Claim 5
Dependent Claim
48 words
The combination of claim 3 wherein the memory cells in said first addressing means storing the address associated with any inlet is scanned a fixed period of time before the scanning of the memory cell in said second addressing means storing the address associated with the same inlet.
Claim 6
Dependent Claim
16 words
The combination of claim 1 further comprising signal regenerating means connecting said demultiplexors to the outlets.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-02-23 | 1979-08-25 | 1980-02-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-02-23 | 1983-08-25 | 1984-02-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-02-23 | 1987-08-25 | 1988-02-24 | $7700.00 | Window Closed / Lapsed |