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US3934335A Expired / Lapsed US ⏱️ 0.0 years remaining

Multilayer printed circuit board

Assignee: Texas Instruments Inc
•
Filing: 1974-10-16
•
Granted: 1976-01-27
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Expires: 1994-10-16
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Abstract

Abstract Multilayer printed circuit board is fabricated by coating a suitable substrate, metal, plastic, paper, with a photosensitive coating, exposing the photosensitive coating to form a dielectric thereof, coating the dielectric layer with a coating of a photosensitive chemical solution, selectively imaging and developing the photosensitive coating to form a desired circuit pattern on the dielectric coating, forming a first layer of circuitry by coating the circuit pattern with a conducting material, coating the circuitry bearing layer with a second layer of photosensitive material, selectively exposing and developing the second layer of photosensitive material to form a dielectric with open windows to the first circuit layer, coating the second dielectric layer of the first circuitry with a coating of photosensitive chemical solution, selectively imaging and developing the coating of photosensitive chemical solution to form a circuit pattern and an interconnect pattern and forming a conductor layer of circuitry and interconnects, the interconnect metallization connecting the second circuitry layer with the first circuitry layer, repeating the process to form additional circuitry layers to perform a desired electrical function and forming on the last dielectric layer a metallization such as either a solder mask for circuit terminals or a ground plane and thereafter either retaining the substrate if desired for, for example, a heat sink or additional support or both, or removing the substrate to form a very light weight multilayer printed circuit board.

Inventors

  • 👤 Mark A. Nelson

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 12:31
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/44; H05K3/445; H05K3/10; H05K3/18; H05K3/181; H05K3/182; H05K3/185; H05K3/22; H05K3/28; H05K3/282; H05K3/46; H05K3/4602; H05K3/4608; H05K1/00; H05K1/02; H05K1/03; H05K1/05; H05K2201/00; H05K2201/09; H05K2201/09209; H05K2201/095; H05K2201/09563; H05K2201/09581; H05K2201/09654; H05K2201/09809; H05K3/0011; H05K3/0017; H05K3/0023; H05K3/0094; H05K3/184; H05K3/30; H05K3/32; H05K3/34; H05K3/3452; H05K3/40; H05K3/42; H05K3/425; H05K3/426; H05K3/429; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49155; Y10T29/49156

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 159 words
A method for fabricating a multilayer printed wiring circuit board comprising: a. forming a dielectric layer on a substrate; b. coating the dielectric layer with a first layer of photosensitive material; c. selectively exposing the first layer of photosensitive material to form a layer defining a first conductor pattern of exposed photosensitive material; d. forming the conductor pattern with a conductor material to form conductors in the conductor pattern; e. coating the circuit bearing layer with a layer of photosensitive substrate material; f. selectively exposing the layer of photosensitive substrate material to form a second dielectric layer defining circuit layer interconnections; g. coating the second dielectric layer with a second layer of photosensitive material; h. selectively exposing the second layer of photosensitive material to form a layer defining a second circuit pattern of exposed photosensitive material; i. forming the second conductor pattern with electrically conducting material; and j. repeating steps e through i to form a plurality of electrically
Claim 2
Independent Claim 159 words
A method for fabricating a multilayer printed wiring circuit board comprising: a. forming a dielectric layer on a substrate; b. coating the dielectric layer with a first layer of photosensitive material; c. selectively exposing the first layer of photosensitive material to form a layer defining a first conductor pattern of exposed photosensitive material; d. forming the conductor pattern with a conductor material to form conductors in the conductor pattern; e. coating the circuit bearing layer with a layer of photosensitive substrate material; f. selectively exposing the layer of photosensitive substrate material to form a second dielectric layer defining circuit layer interconnections; g. coating the second dielectric layer with a second layer of photosensitive material; h. selectively exposing the second layer of photosensitive material to form a layer defining a second circuit pattern of exposed photosensitive material; i. forming the second conductor pattern with electrically conducting material; and j. repeating steps e through i to form a plurality of electrically
Claim 3
Dependent Claim 38 words
A method according to claim 1 further comprising forming apertures of a feed through hole pattern in the substrate prior to forming the dielectric layer on the substrate and coating the holes of the hole pattern with a
Claim 4
Dependent Claim 11 words
A method according to claim 1 wherein the coatings of photosensitive
Claim 5
Dependent Claim 11 words
A method according to claim 1 wherein the coatings of photosensitive
Claim 6
Dependent Claim 11 words
A method according to claim 1 further comprising removing the core
Claim 7
Dependent Claim 11 words
A method according to claim 2 comprising forming the multilayer circuits
Claim 8
Dependent Claim 12 words
A method according to claim 1 further comprising forming a ground plane
Claim 9
Dependent Claim 11 words
A method according to claim 1 further comprising forming a metallization
Claim 10
Dependent Claim 11 words
A method according to claim 8 wherein the desired metallization pattern
Claim 11
Dependent Claim 12 words
A method according to claim 1 further comprising forming a solder mask
Claim 12
Dependent Claim 46 words
A method according to claim 10 wherein the soldering mask comprises selectively coating the outer circuit layer with an epoxy to define areas to be soldered, curing the epoxy layer; and coating the epoxy layer with a protective coating to prevent oxidation of the solder areas.

References Cited (Backward Citations)

US3366519A Cited
US3525617A Cited
US3540954A Cited
US3622384A Cited
US3666549A Cited
US3679941A Cited
US3698940A Cited
US3628999A Cited
US3745095A Cited
US3846166A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1979-01-26 1979-07-28 1980-01-27 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1983-01-26 1983-07-28 1984-01-27 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1987-01-26 1987-07-28 1988-01-27 $7700.00 Window Closed / Lapsed

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