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US3921145A Expired / Lapsed US ⏱️ 0.0 years remaining

Multirequest grouping computer interface

Assignee: Unisys Corp
•
Filing: 1973-10-12
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Granted: 1975-11-18
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Expires: 1993-10-12
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Abstract

Abstract Disclosed is a computer system utilizing an interface unit for controlling coordination among central processor units and a peripheral such as a memory, in a temporal multiplex manner whereby a plurality of requests for access to the memory are clustered for response during a time period prior to grouping of other requests. The system includes at least two independently operable processors and a memory, the latter being connected to the former through the interface, and a positional or other priority resolver operable on a requestor group during the latter''s access time period.

Inventors

  • 👤 Michael Gene Emm
  • 👤 Dongsung Robert Kim

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-22 20:12
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/18

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 178 words
An interface between a plurality of requestors and a requestor priority resolvinG network servicing a responder, the requestors being capable of emitting signals representing the desire for a response, addresses within the responder and information and the responder being capable of emitting signals representing readiness to transmit, information and the end of the information, and the priority resolving network being capable of effectuating sequencing of requestor address-information signals on input lines, one corresponding to each requestor, by energizing its output lines, one corresponding to each requestor, comprising: means responsive to a responder ready signal and a set of requestor response-desired signals made up from at most one from each requester to energize corresponding priority resolving network inputs; means responsive to a responder ready signal to inhibit operation of said energizing means such that a subsequent set of requestor response-desired signals do not affect priority resolving network inputs until all members of a present set are services by the responder; and means responsive to priority resolving network output signals to return a responder information signal to the corresponding requestor.
Claim 2
Dependent Claim 178 words
An interface between a plurality of requestors and a requestor priority resolvinG network servicing a responder, the requestors being capable of emitting signals representing the desire for a response, addresses within the responder and information and the responder being capable of emitting signals representing readiness to transmit, information and the end of the information, and the priority resolving network being capable of effectuating sequencing of requestor address-information signals on input lines, one corresponding to each requestor, by energizing its output lines, one corresponding to each requestor, comprising: means responsive to a responder ready signal and a set of requestor response-desired signals made up from at most one from each requester to energize corresponding priority resolving network inputs; means responsive to a responder ready signal to inhibit operation of said energizing means such that a subsequent set of requestor response-desired signals do not affect priority resolving network inputs until all members of a present set are services by the responder; and means responsive to priority resolving network output signals to return a responder information signal to the corresponding requestor.
Claim 3
Dependent Claim 28 words
The interface of claim 1; and means responsive to responder end-of-information signals to inactivate that portion of said inhibiting means corresponding to a requester serviced by the responder.
Claim 4
Dependent Claim 63 words
The interface of claim 2 wherein said energizing means comprises a set of memory elements, one corresponding to each requestor and connected to receive its response-desired signal, and a set of gates, one corresponding to an input to each of said memory elements, and said inactivating means comprises a set of gates, one corresponding to another input to each of said memory elements.
Claim 5
Dependent Claim 11 words
The interface of claim 3 wherein said memory elements are flip-flops.

References Cited (Backward Citations)

US3308439A Cited
US3407387A Cited
US3395394A Cited
US3603935A Cited
US3638198A Cited
US3648252A Cited
US3710324A Cited
US3701109A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1978-11-17 1979-05-19 1979-11-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1982-11-17 1983-05-19 1983-11-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1986-11-17 1987-05-19 1987-11-18 $7700.00 Window Closed / Lapsed

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