High resolution digitally programmable electronic delay for multi-channel operation

Claim 2

High resolution digitally programmable electronic apparatus for providing an accurately shaped and precisely timed first electrical pulse and an accurately shaped and precisely timed second electrical pulse, said electronic apparatus comprising: a stable first oscillator providing a periodic output at a frequency of f1 megahertz and a clock period of T1 nanoseconds, where f1 is a positive number greater than 100 and T1 is equal to 1/f1; a controllable second oscillator having a control input and providing a periodic output at a frequency of f2 megahertz and a clock period of T2 nanoseconds, where T2 is equal to 1/f2, Nf2 is equal to Mf1, N and M are respectively positive integers and N is not equal to M; phase detector means having first and second inputs and an output; an M radix divider having its input connected to the output of said first oscillator and its output connected to said first input of said phase detector means; an N radix divider having its input connected to the output of said second oscillator and its output connected to said second input of said phase detector means; low pass filter means intercoupling said output of said phase detector means and said control input of said second oscillator; first and second binary counters each having an input, and each having a plurality of outputs respectively designated as 20, 21, 22, 23- - 2n 1 and 2n; binary word manifesting means for manifesting a binary word having bit positions respectively designated 20, 21, 22, 23 - - - - - - 2n 1 and 2n; first comparison means interconnecting said outputs of said first binary counter with said binary word manifesting means, said first comparison means having an output for providing said first electrical pulse when the binary count within said first counter is equal to the binary word manifested by said binary word manifesting means; second comparison means interconnecting outputs of said second binary counter with said binary word manifesting means, said second comparison means having an output for providing said second electrical pulse when the binary count within said second counter is equal to the binary word manifested by said binary word manifesting means; whereby the time duration in nanoseconds between the occurrence of said first electrical pulse and the occurrence of said second electrical pulse is precisely selected and determined by the magnitude of the binary word manifested by said binary word manifesting means.

Claim 3

A high resolution digitally programmable electronic delay for providing an accurately shaped and precisely timed reference pulse and an accurately shaped and precisely timed delay pulse, said electronic delay comprising: a stable pulse generator providing a periodic output at a pulse repetition rate of f1 megahertz and a clock period of T1 nanoseconds, where f1 is a positive number greater than 100 and T1 is equal to 1/f1 nanoseconds; a controllable second pulse generator having a control input and providing a periodic output at a pulse repetition rate of f2 megahertz and a clock period of T2, where T2 is equal to 1/f2, f2 is equal to kf1, and k is a positive constant having a magnitude of less than 2; phase detector means having first and second inPuts and an output; a first divider circuit having its input connected to the output of said first pulse generator and its output connected to said first input of said phase detector means; a second divider circuit having its input connected to the output of said second pulse generator and its output connected to said second input of said phase detector means; means intercoupling said output of said phase detector means and said control input of said second pulse generator; first and second binary counters each having an input and each having an output; binary word manifesting means for manifesting a binary word; first comparison means interconnecting said output of said first binary counter with said binary word manifesting means, said first comparison means having an output for providing said reference pulse when the binary count within said first counter is equal to said binary word manifested by said binary word manifesting means; second comparison means interconnecting said output of said second binary counter with said binary word manifesting means, said second comparison means having an output for providing a said time delayed pulse when the binary count within said second counter is equal to said binary word manifested by said binary manifesting means; whereby the time duration between said reference pulse and said time delayed pulse is precisely selected and determined by the magnitude of the binary word manifested by said binary word manifesting means.

Claim 4

A high resolution digitally programmable electronic delay for providing an accurately shaped and precisely timed reference pulse and an accurately shaped and precisely timed delay pulse, said electronic delay comprising: a stable pulse generator providing a periodic output at a pulse repetition rate of f1 megahertz and a clock period of T1 nanoseconds, where f1 is a positive number greater than 100 and T1 is equal to 1/f1 nanoseconds; a controllable second pulse generator having a control input and providing a periodic output at a pulse repetition rate of f2 megahertz and a clock period of T2, where T2 is equal to 1/f2, f2 is equal to kf1, and k is a positive constant having a magnitude of less than 2; phase detector means having first and second inPuts and an output; a first divider circuit having its input connected to the output of said first pulse generator and its output connected to said first input of said phase detector means; a second divider circuit having its input connected to the output of said second pulse generator and its output connected to said second input of said phase detector means; means intercoupling said output of said phase detector means and said control input of said second pulse generator; first and second binary counters each having an input and each having an output; binary word manifesting means for manifesting a binary word; first comparison means interconnecting said output of said first binary counter with said binary word manifesting means, said first comparison means having an output for providing said reference pulse when the binary count within said first counter is equal to said binary word manifested by said binary word manifesting means; second comparison means interconnecting said output of said second binary counter with said binary word manifesting means, said second comparison means having an output for providing a said time delayed pulse when the binary count within said second counter is equal to said binary word manifested by said binary manifesting means; whereby the time duration between said reference pulse and said time delayed pulse is precisely selected and determined by the magnitude of the binary word manifested by said binary word manifesting means.

Claim 5

A high resolution digitally programmable electronic delay for providing an accurately shaped and precisely timed output pulse a predetermined finite integer number of nanoseconds subsequent to a reference time, said electronic delay comprising: first means for generating said time reference in the form of an electrical pulse; second means for generating said output pulse a predetermined finite integer number of nanoseconds subsequent to said reference time; synchronizing means interconnecting said first and second means for maintaining said second means in synchronism with said first means; and digitally programmable means having input terminals for receiving an electrical manifestation of a digital word and interconnecting said first and second means, said digitally programmable means cooperating with, and controlling said first and second means, whereby the electrical manifestation of a digital word impressed on said input terminals of said digitally programmable means determines the predetermined finite integer number of nanoseconds between said reference time pulse and said accurately shaped and precisely timed output pulse.

Claim 6

A high resolution digitally programmable electronic delay for providing an accurately shaped and precisely timed output pulse a predetermined finite integer number of nanoseconds subsequent to a reference time, said electronic delay comprising: first means for generating said time reference in the form of an electrical pulse; second means for generating said output pulse a predetermined finite integer number of nanoseconds subsequent to said reference time; synchronizing means interconnecting said first and second means for maintaining said second means in synchronism with said first means; and digitally programmable means having input terminals for receiving an electrical manifestation of a digital word and interconnecting said first and second means, said digitally programmable means cooperating with, and controlling said first and second means, whereby the electrical manifestation of a digital word impressed on said input terminals of said digitally programmable means determines the predetermined finite integer number of nanoseconds between said reference time pulse and said accurately shaped and precisely timed output pulse.

Claim 7

Electronic apparatus for providing a first precisely timed pulse and a second precisely timed pulse, where said second pulse is caused to occur precisely 1, 2, 3, 4, 5, 6 or 7 nanoseconds subsequent in time to the rendition of said first pulse, said apparatus including: a first pulse generator providing periodic pulses at a constant pulse repetition rate; a second controllable pulse generator providing periodic pulses at a second controlled pulse repetition rate; control means interconnecting said first and second pulse generators for maintaining a predetermined mathematical relationship between the pulse repetition rate of said second pulse generator and the pulse repetition rate of said first pulse generator; digital means interconnecting said first and second pulse generators, said digital means, receiving first, second, third, fourth, fifth, sixth or seventh distinct digital words, said digital means including means for electrically manifesting said first precisely timed pulse and means for electrically manifesting said second precisely timed pulse, whereby, when said digital means receives said first digital word the time displacement between said first pulse and said second pulse is one nanosecond, when said digital means recieves said second digital word the time displAcement between said first pulse and said second pulse is two nanoseconds, when said digital means receives said third digital word the time displacement between said first pulse and said second pulse is 3 nanoseconds, when said digital means receives said fourth digital word the time displacement between said first pulse and said second pulse is 4 nanoseconds, when said digital means receives said fifth digital word the time displacement between the first and second pulses is 5 nanoseconds, when said digital means receives said sixth digital word the time displacement between said first and second pulses is 6 nanoseconds, and when said digital means receives said seventh digital word the time displacement between said first and second pulses is 7 nanoseconds.

Claim 8

Electronic apparatus for providing a first precisely timed pulse and a second precisely timed pulse, where said second pulse is caused to occur precisely 1, 2, 3, 4, 5, 6 or 7 nanoseconds subsequent in time to the rendition of said first pulse, said apparatus including: a first pulse generator providing periodic pulses at a constant pulse repetition rate; a second controllable pulse generator providing periodic pulses at a second controlled pulse repetition rate; control means interconnecting said first and second pulse generators for maintaining a predetermined mathematical relationship between the pulse repetition rate of said second pulse generator and the pulse repetition rate of said first pulse generator; digital means interconnecting said first and second pulse generators, said digital means, receiving first, second, third, fourth, fifth, sixth or seventh distinct digital words, said digital means including means for electrically manifesting said first precisely timed pulse and means for electrically manifesting said second precisely timed pulse, whereby, when said digital means receives said first digital word the time displacement between said first pulse and said second pulse is one nanosecond, when said digital means recieves said second digital word the time displAcement between said first pulse and said second pulse is two nanoseconds, when said digital means receives said third digital word the time displacement between said first pulse and said second pulse is 3 nanoseconds, when said digital means receives said fourth digital word the time displacement between said first pulse and said second pulse is 4 nanoseconds, when said digital means receives said fifth digital word the time displacement between the first and second pulses is 5 nanoseconds, when said digital means receives said sixth digital word the time displacement between said first and second pulses is 6 nanoseconds, and when said digital means receives said seventh digital word the time displacement between said first and second pulses is 7 nanoseconds.

Claim 9

An electronic timer for accurately defining under control of a digital input 1, 2, 3, 4, 5, 6 or 7 nanosecond periods of elapsed time, said timer comprising: first electronic means providing an output having an invariant time period; second controllable electronic means providing an output having a time period bearing a predetermined fixed mathematical relationship to said invariant time period of said first electronic means; control means intercoupling said first electronic means and said second electronic means, said control means being effective to establish and maintain said fixed mathematical relationship between said time period of said second electronic means and said invariant time period of said first electronic means; digital means having digital input terminals and interconnecting said first and second electronic means, whereby the digital input applied to said digital input terminals of said digital means determines the elapsed time period defined by said electronic timer.

Claim 10

An electronic timer for accurately defining under control of a digital input 1, 2, 3, 4, 5, 6 or 7 nanosecond periods of elapsed time, said timer comprising: first electronic means providing an output having an invariant time period; second controllable electronic means providing an output having a time period bearing a predetermined fixed mathematical relationship to said invariant time period of said first electronic means; control means intercoupling said first electronic means and said second electronic means, said control means being effective to establish and maintain said fixed mathematical relationship between said time period of said second electronic means and said invariant time period of said first electronic means; digital means having digital input terminals and interconnecting said first and second electronic means, whereby the digital input applied to said digital input terminals of said digital means determines the elapsed time period defined by said electronic timer.

Claim 11

A high resolution digitally programmable electronic delay for providing an accurately shaped and precisely timed output electrical pulse, said electronic delay comprising: a stable first oscillator providing a periodic output at a frequency of f1 megahertz and a clock period of T1 nanoseconds, where f1 is a positive number greater than 100 and T1 is equal to 1/f1 nanoseconds; a controllable second oscillator having a control input and providing a periodic output at a frequency of f2 megahertz and a clock period of T2, where T2 is equal to 1/f2 and 9f2 8f1; phase detector means having first and second inputs and an output; an 8 radix divider having its input connected to the output of said first oscillator and its output connected to said first input of said phase detector means; a 9 radix divider having its input connected to the output of said second oscillator and its output connected to said second input of said phase detector means; low pass filter means intercoupling said output of said phase detector means and said control input of said second oscillator; first and second binary bit counters, said first counter having a radix of 8, said second counter having a radix of 9, each of said counters having an input, and each of said counters having outputs respectively designated as the 20, 21 and 22; binary word manifesting means for manifesting a binary word having bit positions respectively designated 2o, 21 and 22; first comparison means interconnecting said 20, 21 and 22 outputs of said first binary counter with said binary word manifesting means, said first comparison means having an output for providing a first electrical pulse when the binary count within said first counter is equal to the binary word manifested by said binary word manifesting means; second comparison means interconnecting said 20, 21 and 22 outputs of said second binary counter with said binary word manifesting means, said second comparison means having an output for providing a second electrical pulse when the binary count within said second counter is equal to said binary word manifested by said binary word manifesting means; whereby the time duration in nanoseconds, between said first electrical pulse and said second electrical pulse is precisely selected and determined by the magnitude of the binary word manifested by said binary word manifesting means.

Claim 12

A high resolution digitally programmable electronic delay for providing an accurately shaped and precisely timed output electrical pulse, said electronic delay comprising: a stable first oscillator providing a periodic output at a frequency of f1 megahertz and a clock period of T1 nanoseconds, where f1 is a positive number greater than 100 and T1 is equal to 1/f1 nanoseconds; a controllable second oscillator having a control input and providing a periodic output at a frequency of f2 megahertz and a clock period of T2, where T2 is equal to 1/f2 and 9f2 8f1; phase detector means having first and second inputs and an output; an 8 radix divider having its input connected to the output of said first oscillator and its output connected to said first input of said phase detector means; a 9 radix divider having its input connected to the output of said second oscillator and its output connected to said second input of said phase detector means; low pass filter means intercoupling said output of said phase detector means and said control input of said second oscillator; first and second binary bit counters, said first counter having a radix of 8, said second counter having a radix of 9, each of said counters having an input, and each of said counters having outputs respectively designated as the 20, 21 and 22; binary word manifesting means for manifesting a binary word having bit positions respectively designated 2o, 21 and 22; first comparison means interconnecting said 20, 21 and 22 outputs of said first binary counter with said binary word manifesting means, said first comparison means having an output for providing a first electrical pulse when the binary count within said first counter is equal to the binary word manifested by said binary word manifesting means; second comparison means interconnecting said 20, 21 and 22 outputs of said second binary counter with said binary word manifesting means, said second comparison means having an output for providing a second electrical pulse when the binary count within said second counter is equal to said binary word manifested by said binary word manifesting means; whereby the time duration in nanoseconds, between said first electrical pulse and said second electrical pulse is precisely selected and determined by the magnitude of the binary word manifested by said binary word manifesting means.

Claim 13

Electronic apparatus for providing a first pulse train wherein the time interval between successive pulses of said first pulse train is consistently a precise integer number of nanoseconds, and a second pulse train wherein the time interval between successive pulses of said second pulse train is consistently a precise integer number of nanoseconds, and wherein each pulse of said second pulse train is displaced in time from a pulse of said first pulse train a predetermined integer number of nanoseconds, said electronic apparatus comprising: first stable pulse generator means for providing said first pulse train; second controllable pulse generator means for providing said second pulse train; and digital means receiving a digital input, said digital means interconnecting said first pulse generator means and said second pulse generator means, said digital means including control means for controlling said second pulse generator means, said control means being responsive to a digital input received by said digital means to determine said predetermined integer number of nanoseconds that each pulse of said second pulse train is displaced in time from a pulse in said first pulse train.

Claim 14

Electronic apparatus for providing a first pulse train wherein the time interval between successive pulses of said first pulse train is consistently a precise integer number of nanoseconds, and a second pulse train wherein the time interval between successive pulses of said second pulse train is consistently a precise integer number of nanoseconds, and wherein each pulse of said second pulse train is displaced in time from a pulse of said first pulse train a predetermined integer number of nanoseconds, said electronic apparatus comprising: first stable pulse generator means for providing said first pulse train; second controllable pulse generator means for providing said second pulse train; and digital means receiving a digital input, said digital means interconnecting said first pulse generator means and said second pulse generator means, said digital means including control means for controlling said second pulse generator means, said control means being responsive to a digital input received by said digital means to determine said predetermined integer number of nanoseconds that each pulse of said second pulse train is displaced in time from a pulse in said first pulse train.

Claim 15

High speed precision electronic apparatus for providing a first pulse at a predetermined time and a second pulse displaced in time from said first pulse any predetermined integer number of nanoseconds, and where said predetermined integer number of nanoseconds is less than 100 nanoseconds, said apparatus comprising: a first stable oscillator providing an output at an invariant frequency; a second controllable oscillator providing an output at a controlled frequency; first digital circuit means coupled to said first oscillator and providing said first pulse, said first digital circuit means receiving a digital input and providing a digital output at a time related to the digital input received by said first digital circuit means; second digital circuit means coupled to said second controllable oscillator and to said first digital circuit means, said second digital circuit means being responsive to said digital output of said first digital circuit means for controlling said second controllable oscillator, said second digital circuit means receiving a digital input and providing said second pulse at a time related to the digital input received by said second digital circuit means; whereby the integer number of nanoseconds that said second pulse is subsequent in time to said first pulse is absolutely determined by the magnitude of the digital input received by said first digital circuit means and the magnitude of the digital input received by said second digital circuit means.

Claim 16

High speed precision electronic apparatus for providing a first pulse at a predetermined time and a second pulse displaced in time from said first pulse any predetermined integer number of nanoseconds, and where said predetermined integer number of nanoseconds is less than 100 nanoseconds, said apparatus comprising: a first stable oscillator providing an output at an invariant frequency; a second controllable oscillator providing an output at a controlled frequency; first digital circuit means coupled to said first oscillator and providing said first pulse, said first digital circuit means receiving a digital input and providing a digital output at a time related to the digital input received by said first digital circuit means; second digital circuit means coupled to said second controllable oscillator and to said first digital circuit means, said second digital circuit means being responsive to said digital output of said first digital circuit means for controlling said second controllable oscillator, said second digital circuit means receiving a digital input and providing said second pulse at a time related to the digital input received by said second digital circuit means; whereby the integer number of nanoseconds that said second pulse is subsequent in time to said first pulse is absolutely determined by the magnitude of the digital input received by said first digital circuit means and the magnitude of the digital input received by said second digital circuit means.

Claim 17

Electronic apparatus for providing a first pulse train having a constant pulse repetition, a second pulse train having a pluse repetition rate euqal to the pulse repetition rate of said first pulse train and where said second pulse train is displaced a controllable integer number of nanoseconds from said first pulse train, said electronic apparatus comprising: first circuit means for providing said first pulse train having a constant repetition rate; second circuit means cooperating with said first circuit means for providing said second pulse train; third circuit means interconnecting said first and second circuit means, said third circuit means including digital control means receiving a digital input for controlling and determining the integer number of nanseconds said second pulse train is displaced from said first pulse train.

Claim 18

Electronic apparatus for providing a first pulse train having a constant pulse repetition, a second pulse train having a pluse repetition rate euqal to the pulse repetition rate of said first pulse train and where said second pulse train is displaced a controllable integer number of nanoseconds from said first pulse train, said electronic apparatus comprising: first circuit means for providing said first pulse train having a constant repetition rate; second circuit means cooperating with said first circuit means for providing said second pulse train; third circuit means interconnecting said first and second circuit means, said third circuit means including digital control means receiving a digital input for controlling and determining the integer number of nanseconds said second pulse train is displaced from said first pulse train.

Claim 19

A high resolution digitally programmable delay circuit for providing a time displaced pulse a precise integer number of elapsed equal time increments with respect to a reference pulse occurring periodically at a precise reference time, where said integer number is any integer from one through one hundred and each said elapsed time increment is of equal duration, and equal to or less than 1 nanosecond, said high resolution digitally programmable delay comprising: a first pulse source for providing output pulses at a constant pulse repetition rate; a first circuit coupled to said first pulse source for providing said periodically occurring reference time pulses; a first pulse counter coupled to said first pulse source, said first pulse counter having a first radix, said first pulse counter having an output manifesting the count contained therein in response to each of said pulses from said first pulse source; a first comparator coupled to said output of said first pulse counter, said first comparator having digital input terminals and an output terminal, said first comparator providing an output when the count contained within said first counter is equal to the digital value impressed on said digital input terminals of said first comparator; a second pulse source for providing output pulses at a controllable pulse repetition rate, said second pulse source having a control input terminal adapted to receive an input for controlling the pulse repetition rate of said second pulse source; a second circuit coupled to said second pulse source and having an output terminal for providing an output having a fixed mathematical relationsip to said pulse repetition rate of said second source; control means intercoupling said control input terminal of said second pulse source, said output terminal of said first comparator and said output terminal of said second circuit, said control means providing said control input for controlling said pulse repetition rate of said second pulse source; a second pulse counter coupled to said second pulse source, said second pulse counter having a second radix, said second pulse counter having an output manifesting the count contained therein in response to each of said pulses from said second pulse source; a second comparator coupled to said output of said second pulse counter, said second comparator having digital input terminals and an output terminal, said second comparator being providing a time displaced pulse when the count contained within said second counter is equal to the digital value impressed on said digital input terminals of said second comparator, whereby said digital value impressed on said digital input terminals of said first comparator and said digital value impressed on said digital input terminals of said second comparator determine the precise integer number of elapsed time increments between said reference time pulses and said time displaced pulses, and the magnitude of an elapsed time increment is mathematically related to the pulse repetition rates of said first and second pulse sources.

Claim 20

A high resolution digitally programmable delay circuit for providing a time displaced pulse a precise integer number of elapsed equal time increments with respect to a reference pulse occurring periodically at a precise reference time, where said integer number is any integer from one through one hundred and each said elapsed time increment is of equal duration, and equal to or less than 1 nanosecond, said high resolution digitally programmable delay comprising: a first pulse source for providing output pulses at a constant pulse repetition rate; a first circuit coupled to said first pulse source for providing said periodically occurring reference time pulses; a first pulse counter coupled to said first pulse source, said first pulse counter having a first radix, said first pulse counter having an output manifesting the count contained therein in response to each of said pulses from said first pulse source; a first comparator coupled to said output of said first pulse counter, said first comparator having digital input terminals and an output terminal, said first comparator providing an output when the count contained within said first counter is equal to the digital value impressed on said digital input terminals of said first comparator; a second pulse source for providing output pulses at a controllable pulse repetition rate, said second pulse source having a control input terminal adapted to receive an input for controlling the pulse repetition rate of said second pulse source; a second circuit coupled to said second pulse source and having an output terminal for providing an output having a fixed mathematical relationsip to said pulse repetition rate of said second source; control means intercoupling said control input terminal of said second pulse source, said output terminal of said first comparator and said output terminal of said second circuit, said control means providing said control input for controlling said pulse repetition rate of said second pulse source; a second pulse counter coupled to said second pulse source, said second pulse counter having a second radix, said second pulse counter having an output manifesting the count contained therein in response to each of said pulses from said second pulse source; a second comparator coupled to said output of said second pulse counter, said second comparator having digital input terminals and an output terminal, said second comparator being providing a time displaced pulse when the count contained within said second counter is equal to the digital value impressed on said digital input terminals of said second comparator, whereby said digital value impressed on said digital input terminals of said first comparator and said digital value impressed on said digital input terminals of said second comparator determine the precise integer number of elapsed time increments between said reference time pulses and said time displaced pulses, and the magnitude of an elapsed time increment is mathematically related to the pulse repetition rates of said first and second pulse sources.

Claim 21

In a high resolution digitally programmable delay circuit for providing a time displaced pulse a precise integer number of elapsed equal time increments with respect to a reference pulse occurring periodically at a precise reference time, as recited in claim 10, where said first pulse source has a clock period of T1 nanoseconds, said second pulse source has a clock period of T2 nanoseconds, T2 is greater in magnitude than T1, and said equal time increments are respectively T2-T1 nansecond in duration.

Claim 22

In a high resolution digitally programmable delay circuit for providing a time displaced pulse a precise integer numbeR of elapsed equal time increments with respect to a reference pulse occurring periodically at a precise reference time, as recited in claim 10, where said first pulse source has a clock period of T1 pico seconds, said second pulse source has a clock period of T2 pico seconds, T2 is greater in magnitude than T1, said equal time increments are respectively T2-T1 pico seconds, and said equal time increments are respectively 100 pico seconds in duration.

Claim 23

In a high resolution digitally programmable delay circuit for providing a time displaced pulse a precise integer number of elapsed equal time increments with respect to a reference pulse occurring periodically at a precise reference time, as recited in claim 11, further characterized in that said digital value impressed on said digital input terminals of said first comparator and said digital value impressed on said digital input terminals of said second comparator are respectively provided by a unitary means in response to a single digital input thereto.

Claim 24

In a high resolution digitally programmable delay circuit for providing a time displaced pulse a precise integer number of elapsed equal time increments with respect to a reference pulse occurring periodically at a precise reference time, as recited in claim 13, further characterized in that said first radix of said first counter is larger than said second radix of said second counter, whereby when said digital value impressed on said digital input terminals of said first comparator is decreased in unison with an increase of said digital value impressed on said digital input terminals of said second comparator said precise integer number of elapsed equal time increments is increased.

Claim 25

In a high resolution digitally programmable delay circuit for providing a time displaced pulse a precise integer number of elapsed equal time increments with respect to a reference pulse occurring periodically at a precise reference time, as recited in claim 11, where said equal time increments as determined by T2-T1 are respectively equal to or less than one-half of a nanosecond in duration.

Claim 26

In a high resolution digitally programmable delay circuit for providing a time displaced pulse a precise integer number of elapsed equal time increments with respect to a reference pulse occurring periodically at a precise reference time, as recited in claim 11, where said equal time increments as determined by T2-T1 are respectively greater than one-half of a nanosecond and less than 1 nanosecond in duration.

Claim 27

In a high resolution digitally programmable delay circuit for providing a time displaced pulse a precise integer number of elapsed equal time increments with respect to a reference pulse occurring periodically at a precise reference time, as recited in claim 10, where the digital values impressed on said digital input terminals of said first comparator, the digital values impressed on said digital input terminals of said second comparator, and said integer number of elapsed time increments are in accordance with the following tabulation:

Claim 28

In a high resolution digitally programmable delay circuit for providing a time displaced pulse a precise iNteger number of elapsed equal time increments with respect to a reference pulse occurring periodically at a precise reference time, as recited in claim 11, where said equal time increments as determined by T2-T1 are respectively equal to, or less than 100 pico seconds in duration.

Claim 29

In high speed precision electronic apparatus for providing a first pulse at a predetermined time and a second pulse displaced in time from said first pulse any predetermined integer number of nanoseconds, as recited in claim 8, where said any predetermined integer number of nanoseconds has a range of 0 through 144.