US3824483A
Expired / Lapsed
US
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Digital device for fast frequency control of a frequency synthesizer
Assignee: Alcatel Lucent NV
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Filing: 1973-07-20
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Granted: 1974-07-16
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Expires: 1993-07-20
Abstract
Abstract This relates to a phase locked loop voltage controlled digital synthesizer in which digital pulses produced from a voltage controlled oscillator (VCO) and a first frequency divider and a reference oscillator and a second frequency divider are applied to a comparator which produces an output signal when the compared pulses have repetition frequencies which are not equal. The comparator output signal results in a voltage which is applied to the VCO to change the frequency thereof in steps until repetition frequency equality is achieved. The purpose of the present invention is to shorten the time needed to cause the repetition frequency of the pulses at the output of the first frequency divider to equal the repetition frequency of the pulses at the output of the second frequency divider. This is accomplished by including a reversible counter connected to the comparator output. The output signal of the reversible counter is connected to a digital-to-analog converter to produce the VCO control voltage. In addition, two other control circuits are provided for each of the first frequency divider and the second frequency divider which cooperate with the reversible counter in reducing the time of achieving repetition frequency equality.
Inventors
- 👤 J Margala
- 👤 J Cassany
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 05:37
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/183; H03L7/191
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
310 words
A digital device for frequency control of a frequency synthesizer comprising: a voltage controlled oscillator to produce pulses having a frequency control input; a first counter-divider having a variable division ratio, an input, an output and a reset input; a highly stabilized oscillator to produce pulses; a second counter-divider having a given division ratio, an input, an output and a reset input; a frequency comparator having two inputs, an up count output, a down count output and two reset outputs, each of said inputs of said comparator being coupled to said output of a different one of said first and second counter-divider; a reversible counter having an up count input coupled to said up count output of said comparator, a down count input coupled to said down count output of said comparator and outputs; a digital-to-analog converter having inputs coupled to said outputs of said reversible counter and an output coupled to said control input of said voltage controlled oscillator; first means coupled between the output of said voltage controlled oscillator and said input of said first counterdivider and coupled to said output of said first counterdivider to provide input pulses to be frequency divided by said first counTer-divider; second means coupled between the output of said stabilized oscillator and said input of said second counter-divider and coupled to said output of said second counter-divider to provide input pulses to be frequency divided by said second counter-divider; third means coupled between the output of said voltage controlled oscillator and said reset input of said first counter-divider and coupled to one of said two reset outputs of said comparator to reset said first counter-divider; and fourth means coupled between the output of said stabilized oscillator and said reset input of said second counter-divider and coupled to the other of said two reset outputs of said comparator to reset said second counter-divider.
Claim 2
Dependent Claim
310 words
A digital device for frequency control of a frequency synthesizer comprising: a voltage controlled oscillator to produce pulses having a frequency control input; a first counter-divider having a variable division ratio, an input, an output and a reset input; a highly stabilized oscillator to produce pulses; a second counter-divider having a given division ratio, an input, an output and a reset input; a frequency comparator having two inputs, an up count output, a down count output and two reset outputs, each of said inputs of said comparator being coupled to said output of a different one of said first and second counter-divider; a reversible counter having an up count input coupled to said up count output of said comparator, a down count input coupled to said down count output of said comparator and outputs; a digital-to-analog converter having inputs coupled to said outputs of said reversible counter and an output coupled to said control input of said voltage controlled oscillator; first means coupled between the output of said voltage controlled oscillator and said input of said first counterdivider and coupled to said output of said first counterdivider to provide input pulses to be frequency divided by said first counTer-divider; second means coupled between the output of said stabilized oscillator and said input of said second counter-divider and coupled to said output of said second counter-divider to provide input pulses to be frequency divided by said second counter-divider; third means coupled between the output of said voltage controlled oscillator and said reset input of said first counter-divider and coupled to one of said two reset outputs of said comparator to reset said first counter-divider; and fourth means coupled between the output of said stabilized oscillator and said reset input of said second counter-divider and coupled to the other of said two reset outputs of said comparator to reset said second counter-divider.
Claim 3
Dependent Claim
120 words
A device according to claim 1, wherein each of said first and second means include a first delay flip flop having an output, a data input coupled to said output of an associated one of said first and second counter-dividers and a clock input coupled to the output of an associated one of said voltage controlled oscillator and said stabilized oscillator, and a two input AND gate having one of its inputs coupled to the output an associated one of said voltage controlled oscillator and said stabilized oscillator, the other of its inputs coupled to said output of said first delay flip flop and its output coupled to said input of an associated one of said first and second counter-dividers.
Claim 4
Dependent Claim
212 words
A device according to claim 2, wherein said comparator includes a J-K flip flop having a J input, a K input, a Q output and a Q output, said J input being coupled to said output of said first counter-divider and said K input being coupled to said output of said second counter-divider, a first two input OR gate having one of its inputs coupled to said output of said first counter-divider, the other of its inputs coupled to said Q output and its output coupled to said third means, a second two input OR gate having one of its inputs coupled to said output of said second counter-divider, the other of its inputs coupled to said Q output and its output coupled to said fourth means, a third two input OR gate having one of its inputs coupled to said output of said first counter-divider, the other of its inputs coupled to said Q output and its output coupled to said up count input of said reversible counter, and a fourth two input OR gate having one of its inputs coupled to said output of said second counter-divider, the other of its inputs coupled to said Q output and its output coupled to said down count input of said reversible counter.
Claim 5
Dependent Claim
77 words
A device according to claim 3, wherein each of said third and fourth means include a second delay flip flop having a data input coupled to the output of an associated one of said first and second OR gates, a clock input coupled to the output of an associated one of said voltage controlled oscillator and said stabilized oscillator and an output coupled to said reset input of an associated one of said first and second counter-dividers.
Claim 6
Dependent Claim
212 words
A device according to claim 1, wherein said comparator includes a J-K flip flop having a J input, a K input, a Q output and a Q output, said J input being coupled to said output of said first counter-divider and said K input being coupled to said output of said second counter-divider, a first two input OR gate having one of its inputs coupled to said output of said first counter-divider, the other of its inputs coupled to said Q output and its output coupled to said third means, a second two input OR gate having one of its inputs coupled to said output of said second counter-divider, the other of its inputs coupled to said Q output and its output coupled to said fourth means, a third two input OR gate having one of its inputs coupled to said output of said first counter-divider, the other of its inputs coupled to said Q output and its output coupled to saId up count input of said reversible counter, and a fourth two input OR gate having one of its inputs coupled to said output of said second counter-divider, the other of its inputs coupled to said Q output and its output coupled to said down count input of said reversible counter.
Claim 7
Dependent Claim
77 words
A device according to claim 5, wherein each of said third and fourth means include a second delay flip flop having a data input coupled to the output of an associated one of said first and second OR gates, a clock input coupled to the output of an associated one of said voltage controlled oscillator and said stabilized oscillator and an output coupled to said reset input of an associated one of said first and second counter-dividers.
Claim 8
Dependent Claim
74 words
A device according to claim 1, wherein each of said third and fourth means include a delay flip flop having a date input coupled to an associated one of said two other outputs of said comparator, a clock input coupled to the output of an associated one of said voltage controlled oscillator and said stabilized oscillator and an output coupled to said reset input of an associated one of said first and second counter-dividers.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-07-15 | 1978-01-14 | 1978-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-07-15 | 1982-01-14 | 1982-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-07-15 | 1986-01-14 | 1986-07-16 | $7700.00 | Window Closed / Lapsed |