US3766524A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic time slicing control for microprogrammed controller
Assignee: International Business Machines Corp
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Filing: 1971-06-30
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Granted: 1973-10-16
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Expires: 1991-06-30
Abstract
Abstract A plurality of independent addressing devices are dynamically assigned instruction cycles. The addressing devices each address a common addressable data storage unit. Logic circuitry is provided to generate status signals indicating which addressing device is active during a present instruction cycle. Other logic circuitry is responsive to interrupt requests to generate signals indicating the status of competing interrupts. Instruction cycle assignment circuitry is responsive to the active address device status signals and the interrupt status signals to generate signals for selecting the addressing device which is to be assigned the next instruction cycle.
Inventors
- 👤 L Rust
- 👤 B Maring
- 👤 J Nicholson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:07
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F13/26; G06F9/00; G06F9/06; G06F9/22; G06F9/26; G06F9/262; G06F9/268
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
115 words
In a data processing system including a cyclically operating storage means containing a sequence of instructions for controlling the allocation of instruction cycles to service a plurality of dissimilar interrupts, the improvement comprising: a. means coupled to said storage means and responsive to a first interrupt associated with a first device for dynamically assigning consecutive instruction cycles of said storage means to said first device; and b. means coupled to said storage means and responsive to the simultaneous occurrence of said first interrupt and a second or multiple interrupt associated with a second or multiple device for dynamically assigning alternate consecutive instruction cycles of said storage means to said first and second or multiple devices.
Claim 2
Dependent Claim
115 words
In a data processing system including a cyclically operating storage means containing a sequence of instructions for controlling the allocation of instruction cycles to service a plurality of dissimilar interrupts, the improvement comprising: a. means coupled to said storage means and responsive to a first interrupt associated with a first device for dynamically assigning consecutive instruction cycles of said storage means to said first device; and b. means coupled to said storage means and responsive to the simultaneous occurrence of said first interrupt and a second or multiple interrupt associated with a second or multiple device for dynamically assigning alternate consecutive instruction cycles of said storage means to said first and second or multiple devices.
Claim 3
Dependent Claim
57 words
The improvement as defined in claim 1 further comprising means operatively connected to said storage means and responsive to the simultaneous occurrence of said first interrupt, said second interrupt and a plurality of other interrupts respectively associated with other devices for sequentially assigning consecutive instruction cycles of said storage means to said first, second and other devices.
Claim 4
Dependent Claim
39 words
The improvement as defined in claim 1 further comprising means coupled to said storage means for normally assigning consecutive instruction cycles of said storage means to said second device in the absence of said first and second interrupt commands.
Claim 5
Dependent Claim
109 words
In a data processing system including a cyclically operating storage means containing a sequence of instructions for controlling the operation of a plurality of devices, the improved method of assigning priorities to determine which device is to be serviced by the storage means comprising the steps of: a. dynamically consecutive instruction cycles of said storage means to a first device in response to a high priority service rEquest from said first device; and b. consecutive dynamically assigning alternate instruction cycles of said storage means to said first device and to a second device upon the simultaneous occurrence of high priority service requests from both said first and second devices.
Claim 6
Dependent Claim
109 words
In a data processing system including a cyclically operating storage means containing a sequence of instructions for controlling the operation of a plurality of devices, the improved method of assigning priorities to determine which device is to be serviced by the storage means comprising the steps of: a. dynamically consecutive instruction cycles of said storage means to a first device in response to a high priority service rEquest from said first device; and b. consecutive dynamically assigning alternate instruction cycles of said storage means to said first device and to a second device upon the simultaneous occurrence of high priority service requests from both said first and second devices.
Claim 7
Dependent Claim
36 words
The improved method as defined in claim 4 further comprising assigning consecutive instruction cycles of said storage means to one of said devices in the absence of high priority service requests from either of said devices.
Claim 8
Dependent Claim
46 words
The improved method as defined in claim 4 further comprising sequentially assigning consecutive instruction cycles of said storage means to said first and said second devices and to other devices upon the simultaneous occurrence of high priority service requests from said first, second and other devices.
Claim 9
Dependent Claim
85 words
In a data processing apparatus, a method for dynamically allocating instruction cycles to a plurality of addressing means for addressing an addressable storage unit in response to multiple interrupts having an unpredictable arrival pattern comprising: circuits to electronically determining which of said plurality of addressing means is active during an instruction cycle, circuits to electronically determining the status of interrupts requesting instructions stored in said storage unit, and circuits to one of the addressing means to be used next based upon the results of determinations.
Claim 10
Dependent Claim
85 words
In a data processing apparatus, a method for dynamically allocating instruction cycles to a plurality of addressing means for addressing an addressable storage unit in response to multiple interrupts having an unpredictable arrival pattern comprising: circuits to electronically determining which of said plurality of addressing means is active during an instruction cycle, circuits to electronically determining the status of interrupts requesting instructions stored in said storage unit, and circuits to one of the addressing means to be used next based upon the results of determinations.
Claim 11
Dependent Claim
114 words
In a data processing system, apparatus for allocating instruction cycles selectively one at a time in sequence to one of a plurality of addressing means for addressing addressable storage means each addressing means being used for operating a logical program for servicing interrupts having a nonpredictable occurrence pattern comprising: first sensing means operatively connected to said addressing means for determining which addressing means is currently active during each instruction cycle; second sensing means for sensing interrupt request status during each instruction cycle; and third means for determining to which of said addressing means the next instruction cycle is to be assigned in response to the conditions sensed by said first and second sensing means.
Claim 12
Dependent Claim
114 words
In a data processing system, apparatus for allocating instruction cycles selectively one at a time in sequence to one of a plurality of addressing means for addressing addressable storage means each addressing means being used for operating a logical program for servicing interrupts having a nonpredictable occurrence pattern comprising: first sensing means operatively connected to said addressing means for determining which addressing means is currently active during each instruction cycle; second sensing means for sensing interrupt request status during each instruction cycle; and third means for determining to which of said addressing means the next instruction cycle is to be assigned in response to the conditions sensed by said first and second sensing means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-15 | 1977-04-16 | 1977-10-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-15 | 1981-04-16 | 1981-10-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-15 | 1985-04-16 | 1985-10-16 | $7700.00 | Window Closed / Lapsed |