Patent US4371932A successfully refreshed from Google Patents.
Patent US3909790A successfully refreshed from Google Patents.
US3909790A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Minicomputer with selector channel input-output system and interrupt system
Assignee: OMNUS COMPUTER CORP
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Filing: 1972-08-25
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Granted: 1975-09-30
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Expires: 1992-08-25
Abstract
Abstract A single buss minicomputer for use in a data processing system including a plurality of input-output devices. In the first part of the invention, execution of a special instruction by the computer enables a designated one of the input-output devices and connects it to the system to either transmit or receive data. All subsequent communications to and from the computer are with the designated device until the special instruction is again executed, enabling a different input-output device. The special instruction may originate from within the computer memory in a stored program or may be inputted to the system from one of the input-output devices via an interrupt system, the second part of the invention. The interrupt system allows any of the inputoutput devices to notify the minicomputer when servicing of any kind is required. Following an interrupt priority determination, the interrupting input-output device is connected to the system until a subsequent higher priority interrupt is received, the interrupt servicing is completed or a special connect instruction is executed to enable a different input-output device. A most important aspect of the interrupt system of this invention is that the interrupting input-output device can input instructions directly to the minicomputer. Via the interrupt system, then, any input-output device can input instructions directly to the instruction register of the central processing unit for execution.
Inventors
- 👤 Allen L Shapiro
- 👤 Douglas T Sherwood
- 👤 Shelton A Foster
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 20:10
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F12/00; G06F12/02; G06F12/06; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F13/26
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
205 words
In a data processing system in which information units are transferred between a computer in the system and a plurality of input-output devices, the combination comprising computer means, means for transferring units of information to and from said computer means, a plurality of input-output devices, a plurality of controller means, each connected to said transferring means and one of said plurality of input-output devices, each of said controller means comprising means connected to said transferring means for decoding units of information transferred thereby and generating an enabling signal when an information unit having a predetermined content is decoded, register means connected to receive said enabling signal and connected to said transferring means for developing a plurality of control outputs, one of said control outputs being turned on in response to an information unit transferred on said transferring means subsequent to said unit having a predetermined content when the register means is enabled by said enabling signal, a plurality of means for selectively transmitting information units between said means for transferring and the input-output device connected to said controller means, and, means connecting each of said register control outputs to one of said transmitting means for controlling said means to transmit or not transmit information units.
Claim 2
Dependent Claim
205 words
In a data processing system in which information units are transferred between a computer in the system and a plurality of input-output devices, the combination comprising computer means, means for transferring units of information to and from said computer means, a plurality of input-output devices, a plurality of controller means, each connected to said transferring means and one of said plurality of input-output devices, each of said controller means comprising means connected to said transferring means for decoding units of information transferred thereby and generating an enabling signal when an information unit having a predetermined content is decoded, register means connected to receive said enabling signal and connected to said transferring means for developing a plurality of control outputs, one of said control outputs being turned on in response to an information unit transferred on said transferring means subsequent to said unit having a predetermined content when the register means is enabled by said enabling signal, a plurality of means for selectively transmitting information units between said means for transferring and the input-output device connected to said controller means, and, means connecting each of said register control outputs to one of said transmitting means for controlling said means to transmit or not transmit information units.
Claim 3
Dependent Claim
30 words
The combination of claim 1, wherein said means for transferring units of information comprises bidirectional buss means foR transferring data, control and instruction words to and from said computer means.
Claim 4
Dependent Claim
56 words
The combination of claim 1, wherein said means for decoding comprises, logic circuit means for determining the presence on said transferring means of an information unit having a predetermined content and for developing a setting output signal in response thereto, and, bistable circuit means for developing an enabling signal in response to said setting output signal.
Claim 5
Dependent Claim
35 words
The combination of claim 3, further comprising second logic circuit means connected to said transferring means and to a computer control signal for developing a second setting output signal connected to said bistable circuit means.
Claim 6
Dependent Claim
39 words
The combination of claim 1, wherein said register means develops a plurality of outputs for determining whether information units are to be transferred from said computer means to said input-output device or from said device to said computer means.
Claim 7
Dependent Claim
17 words
The combination of claim 1, wherein said means for selectively transmitting information units comprises buffer storage means.
Claim 8
Dependent Claim
25 words
The combination of claim 1, wherein said means for selectively transmitting information units comprises means for generating program instructions for execution by said computer means.
Claim 9
Dependent Claim
35 words
The combination of claim 7, wherein said connecting means comprises gate means controlled by one of said register control outputs for causing program instructions to be transferred to said computer means by said transferring means.
Claim 10
Dependent Claim
62 words
The combination of claim 1, further comprising means for generating an interrupt signal from said input-output device connected to said controller means, means connecting said interrupt signal to said register means for controlling said register means to develop an instruction control output, and, means controlled by said instruction control output for generating an instruction information unit for execution by said computer means.
Claim 11
Dependent Claim
17 words
The combination of claim 9, further comprising means connecting said instruction information unit to said transferring means.
Claim 12
Dependent Claim
24 words
The combination of claim 9, further comprising means for generating an information unit having said predetermined content in response to said instruction information unit.
Claim 13
Dependent Claim
31 words
The combination of claim 9, further comprising means connected to all means for generating interrupt signals for determining the priority between interrupts if more than one interrupt signal is generated simultaneously.
Claim 14
Dependent Claim
89 words
The combination of claim 1, further comprising means for generating an interrupt signal from said input-output device connected to said controller means, means connecting said interrupt signal to said register means for controlling said register means to develop an instruction control output, means controlled by said instruction control output for generating an instruction information unit for execution by said computer means, means connecting said instruction information unit to said transferring means, and, means for generating an information unit of said predetermined content in response to said instruction information unit.
Claim 15
Dependent Claim
245 words
In a data processing system in which information units are transferred between a computer in the system and a plurality of input-output devices, the combination comprising computer means, means for transferring units of information to and from said computer means, a plurality of input-output devices, a plurality of controller means, each connected to said transferring means and one of said plurality of input-output devices, each of said controller means comprising logic circuit means for determining the presence on said transferring means of an information unit of predetermined content and for developing a setting output signal in response thereo, bistable circuit means for developing an enabling signal in response to said setting output signal, register means connected to receive said enabling signal and conNected to said transferring means for developing a plurality of control outputs for determining whether information units are to be transferred from said computer means to said input-output device or from said device to said computer means, one of said control outputs being turned on in response to an information unit transferred on said transferring means subsequent to said unit having a predetermined content when the register means is enabled by said enabling signal, a plurality of means for selectively transmitting information units between said means for transferring and the input-output device connected to said controller means, and, means connecting each of said register control outputs to one of said transmitting means for controlling said means to transmit or not transmit information units.
Claim 16
Dependent Claim
245 words
In a data processing system in which information units are transferred between a computer in the system and a plurality of input-output devices, the combination comprising computer means, means for transferring units of information to and from said computer means, a plurality of input-output devices, a plurality of controller means, each connected to said transferring means and one of said plurality of input-output devices, each of said controller means comprising logic circuit means for determining the presence on said transferring means of an information unit of predetermined content and for developing a setting output signal in response thereo, bistable circuit means for developing an enabling signal in response to said setting output signal, register means connected to receive said enabling signal and conNected to said transferring means for developing a plurality of control outputs for determining whether information units are to be transferred from said computer means to said input-output device or from said device to said computer means, one of said control outputs being turned on in response to an information unit transferred on said transferring means subsequent to said unit having a predetermined content when the register means is enabled by said enabling signal, a plurality of means for selectively transmitting information units between said means for transferring and the input-output device connected to said controller means, and, means connecting each of said register control outputs to one of said transmitting means for controlling said means to transmit or not transmit information units.
Claim 17
Dependent Claim
62 words
The combination of claim 14, further comprising means for generating an interrupt signal from said input-output device connected to said controller means, means connecting said interrupt signal to said register means for controlling said register means to develop an instruction control output, and, means controlled by said instruction control output for generating an instruction information unit for execution by said computer means.
Claim 18
Dependent Claim
17 words
The combination of claim 15, further comprising means connecting said instruction information unit to said transferring means.
Claim 19
Dependent Claim
24 words
The combination of claim 15, further comprising means for generating an information unit of said predetermined content in response to said instruction information unit.
Claim 20
Dependent Claim
31 words
The combination of claim 15, further comprising means connected to all means for generating interrupt signals for determining the priority between interrupts if more than one interrupt signal is generated simultaneously.
Claim 21
Dependent Claim
89 words
The combination of claim 14, further comprising, means for generating an interrupt signal from said input-output device connected to said controller means, means connecting said interrupt signal to said register means for controlling said register means to develop an instruction control output, means controlled by said instruction control output for generating an instruction information unit for execution by said computer means, means connecting said instruction information unit to said transferring means, and, means for generating an information unit of said predetermined content in response to said instruction information unit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-09-29 | 1979-03-31 | 1979-09-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-09-29 | 1983-03-31 | 1983-09-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-09-29 | 1987-03-31 | 1987-09-30 | $7700.00 | Window Closed / Lapsed |