US3883867A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Information input device
Assignee: Omron Corp
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Filing: 1973-04-04
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Granted: 1975-05-13
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Expires: 1993-04-04
Abstract
Abstract An information input device comprising a plurality of switches, each of which is operated by an external instruction, and an input circuit for processing signals fed from any one of said switches by means of input lines which are provided for connecting the switches and the input circuit through input terminals, wherein number of the input terminals are advantageously reduced to a small number. To this end, timing signals generated in different times are applied to the respective input lines, and each of the switches connecting to a pair of any two of the input lines. The input circuit receives signals fed respectively from the input lines so as to generate coded signals, representing one of the switches that has received the external instruction, in response to variation of the state occurring on the input lines in timings relating to the timing signals applied to two of the input lines to which the switch having received the external instruction is inserted.
Inventors
- 👤 Isao Hatano
- 👤 Akira Nagano
- 👤 Kazuaki Urasaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 08:11
CPC Classifications
H; H03; H03M; H03M11/00; H03M11/20
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
287 words
An information input device which comprises means for generating a plurality of timing signals in different timings, a plurality of input lines connected with said generating means for respectively receiving the timing signals generated thereby, a plurality of key contacts, each of said key contacts beIng connected between a different pair of said input lines and operable in response to an external instruction applied thereto, a first NAND gate connected with each of said input lines, a first flip-flop being set by one of said timing signals and reset by an output from said first NAND gate, a second flip-flop being set by said one of said timing signals and reset by said output from said NAND gate generated after said first flip-flop has been set, a second NAND gate having a first terminal adapted to receive a bit timing signal having the 21s and 22s weights and a second terminal adapted to receive a set output from said first flip-flop, a third NAND gate adapted to receive a reset output from said first flip-flop, a set output from said second flipflop and a bit timing signal having the 20s weight, a fourth NAND gate adapted to receive an output from said second NAND gate and an output from said third NAND gate, a first AND gate adapted to receive an output from said fourth NAND gate, a full adder adapted to receive an output from said first AND gate, a shift register for storing an output from said full adder, gating means for supplying an output from said shift register to said full adder independent of said output from said first AND gate, and gating circuit for reading out the content stored in said shift register.
Claim 2
Dependent Claim
287 words
An information input device which comprises means for generating a plurality of timing signals in different timings, a plurality of input lines connected with said generating means for respectively receiving the timing signals generated thereby, a plurality of key contacts, each of said key contacts beIng connected between a different pair of said input lines and operable in response to an external instruction applied thereto, a first NAND gate connected with each of said input lines, a first flip-flop being set by one of said timing signals and reset by an output from said first NAND gate, a second flip-flop being set by said one of said timing signals and reset by said output from said NAND gate generated after said first flip-flop has been set, a second NAND gate having a first terminal adapted to receive a bit timing signal having the 21s and 22s weights and a second terminal adapted to receive a set output from said first flip-flop, a third NAND gate adapted to receive a reset output from said first flip-flop, a set output from said second flipflop and a bit timing signal having the 20s weight, a fourth NAND gate adapted to receive an output from said second NAND gate and an output from said third NAND gate, a first AND gate adapted to receive an output from said fourth NAND gate, a full adder adapted to receive an output from said first AND gate, a shift register for storing an output from said full adder, gating means for supplying an output from said shift register to said full adder independent of said output from said first AND gate, and gating circuit for reading out the content stored in said shift register.
Claim 3
Dependent Claim
223 words
An information input device which comprises means for generating a plurality of timing signals different from one another, a plurality of input lines connected with said generating means for respectively receiving the timing signals generated from said generating means, a plurality of switches, each of said switches being connected between a different pair of said input lines and operable in response to an external instruction applied thereto, NAND gate means connected with said input lines for reading out first and second timing signals fed through any pair of said input lines in which one of said switches that has been operated is connected, means for producing first and second periods defined by said first and second timing signals and a third timing signal different from said first and second timing signals, means for generating a digital signal having a value of Alpha , means for generating a digital signal having a value of Beta , calculating means for adding the value Alpha at every timing period of said timing signal generating means during said first period and for adding the value Beta during said second period, and a register means which is cleared before said first period for storing the resultant of the addition of said calculating means, the resultant being a signal coded in correspondence with said switch that has been operated.
Claim 4
Dependent Claim
223 words
An information input device which comprises means for generating a plurality of timing signals different from one another, a plurality of input lines connected with said generating means for respectively receiving the timing signals generated from said generating means, a plurality of switches, each of said switches being connected between a different pair of said input lines and operable in response to an external instruction applied thereto, NAND gate means connected with said input lines for reading out first and second timing signals fed through any pair of said input lines in which one of said switches that has been operated is connected, means for producing first and second periods defined by said first and second timing signals and a third timing signal different from said first and second timing signals, means for generating a digital signal having a value of Alpha , means for generating a digital signal having a value of Beta , calculating means for adding the value Alpha at every timing period of said timing signal generating means during said first period and for adding the value Beta during said second period, and a register means which is cleared before said first period for storing the resultant of the addition of said calculating means, the resultant being a signal coded in correspondence with said switch that has been operated.
Claim 5
Dependent Claim
22 words
An information input device as claimed in claim 2, wherein said values Alpha and Beta are six (6) and one (1), respectively.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-12 | 1978-11-11 | 1979-05-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-12 | 1982-11-11 | 1983-05-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-12 | 1986-11-11 | 1987-05-13 | $7700.00 | Window Closed / Lapsed |