← Back to Patent Explorer
US3877025A Expired / Lapsed US ⏱️ 0.0 years remaining

Analog to digital converter of the parallel comparison

Assignee: Hitachi Ltd
•
Filing: 1973-09-28
•
Granted: 1975-04-08
•
Expires: 1993-09-28
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract An analog-to-digital converter for converting at a high rate an analog input signal into a digital signal by comparing it with a predetermined reference voltage parallelly. The converter comprises a plurality of parallel-connected comparators having window type comparison characteristics and each of which produces a binary-code signal of "1" or "0" only when the analog input signal is at a value within a window, that is, between a couple of reference voltages predetermined for respective comparators, and a code converter for converting the parallel output signals from the comparators into a series of binary-code signals having a predetermined number of bits.

Inventors

  • 👤 Kenji Maio

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 04:31
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/36; H03M1/361

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 217 words
An analog-to-digital converter of parallel comparison type comprising a plurality of comparator means each producing a binary-code signal of a predetermined level only when an analog input signal applied to said comparator means is between two reference voltages predetermined for said comparator means, said reference voltages being predetermined in a multiplicity of stages corresponding to the quantization of the analog input signals, said reference voltages being applied to respective comparator means being different from one another, and code conversion means for converting parallel binary-code signals obtained from said comparator means into a series of binary-code signals having the number of bits related to the number of quantization levels, said plurality of comparator means including a plurality of differential comparators and a plurality of output transistors each inserted between two adjacent differential comparators, each of said differential comparators including at least two transistors, each of said output transistors having an emitter connected to the collector of one of the two transistors of the first of the adjacent differential comparators and having a base connected to the collector of one of the two transistors of the second of the adjacent differential comparators, said output transistors being turned on and off by the potential differences of the collector outputs of said two differential comparators, thereby forming window type comparison characteristics.
Claim 2
Dependent Claim 217 words
An analog-to-digital converter of parallel comparison type comprising a plurality of comparator means each producing a binary-code signal of a predetermined level only when an analog input signal applied to said comparator means is between two reference voltages predetermined for said comparator means, said reference voltages being predetermined in a multiplicity of stages corresponding to the quantization of the analog input signals, said reference voltages being applied to respective comparator means being different from one another, and code conversion means for converting parallel binary-code signals obtained from said comparator means into a series of binary-code signals having the number of bits related to the number of quantization levels, said plurality of comparator means including a plurality of differential comparators and a plurality of output transistors each inserted between two adjacent differential comparators, each of said differential comparators including at least two transistors, each of said output transistors having an emitter connected to the collector of one of the two transistors of the first of the adjacent differential comparators and having a base connected to the collector of one of the two transistors of the second of the adjacent differential comparators, said output transistors being turned on and off by the potential differences of the collector outputs of said two differential comparators, thereby forming window type comparison characteristics.
Claim 3
Dependent Claim 32 words
An analog-to-digital converter according to claim 1, wherein said plurality of differential comparators are equal in number to(n + 1) /2 where the numer of quantization levels n is an odd number.
Claim 4
Dependent Claim 30 words
An analog-to-digital converter according to claim 1, wherein said plurality of differential comparators are equal in number to n/2 where the number of quantization levels n is an even number.
Claim 5
Dependent Claim 131 words
An analog-to-digital converter of parallel comparison type comprising a plurality of comparator means each producing a binary-code output signal of a predetermined level only when an analog input signal applied to said comparator means is between two reference voltages predetermined for said comparator means, said comparator means each having two comparators including at least a part of an output circuit section common to said two comparators, said reference voltages being predetermined in a multiplicity of stages corresponding to the quantization levels of the analog input signals, the reference voltages applied to respective comparator means being different from one another, and code conversion means for converting parallel binary-code signals obtained from said comparator means into a series of binary-code signals having the number of bits related to the number of quantization levels.
Claim 6
Dependent Claim 131 words
An analog-to-digital converter of parallel comparison type comprising a plurality of comparator means each producing a binary-code output signal of a predetermined level only when an analog input signal applied to said comparator means is between two reference voltages predetermined for said comparator means, said comparator means each having two comparators including at least a part of an output circuit section common to said two comparators, said reference voltages being predetermined in a multiplicity of stages corresponding to the quantization levels of the analog input signals, the reference voltages applied to respective comparator means being different from one another, and code conversion means for converting parallel binary-code signals obtained from said comparator means into a series of binary-code signals having the number of bits related to the number of quantization levels.
Claim 7
Dependent Claim 15 words
An analog-to-digital converter according to claim 4, wherein said comparator means are dual type comparators.

References Cited (Backward Citations)

US3277463A Cited
US3585635A Cited
US3597761A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1978-04-07 1978-10-07 1979-04-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1982-04-07 1982-10-07 1983-04-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1986-04-07 1986-10-07 1987-04-08 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag