US3585635A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Analog-to-digital converter
Assignee: AT&T Inc
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Filing: 1968-12-23
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Granted: 1971-06-15
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Expires: 1988-12-23
Abstract
Abstract Parallel transistor-resistor combinations are respectively connected into two conduction paths supplied by a constant current source, and a sampled analog input signal is applied in common to the base terminals of the transistors. Voltage pairs defining predetermined voltage intervals are applied to the respective emitters of the transistors such that one of the transistors is turned ON if the input signal is within one of the predetermined voltage intervals. A difference circuit bridged across the collectors of the transistors yields an output representative of a binary digit.
Inventors
- 👤 Paul A Reiling
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 05:28
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/22
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
166 words
In an analog-to-digital converter, at least one decision circuit comprising: first and second conduction paths, first and second impedance means serially included respectively in said first and second conduction paths, first means connected in parallel with said first impedance means and having a first input voltage terminal, the operation of said first means shunting said first impedance means, second means connected in parallel with said second impedance means and having a second input voltage terminal, the operation of said second means shunting said second impedance means, a common input terminal connected to said first and second input voltage terminals, difference output means connected to said first and second conduction paths, and means for supplying constant current connected to said first and second conduction paths; and waveform generation means connected to said first and second conduction paths for selectively operating one of said first and second means when a voltage applied to said common input terminal is within one of a plurality of predetermined intervals of voltage.
Claim 2
Dependent Claim
166 words
In an analog-to-digital converter, at least one decision circuit comprising: first and second conduction paths, first and second impedance means serially included respectively in said first and second conduction paths, first means connected in parallel with said first impedance means and having a first input voltage terminal, the operation of said first means shunting said first impedance means, second means connected in parallel with said second impedance means and having a second input voltage terminal, the operation of said second means shunting said second impedance means, a common input terminal connected to said first and second input voltage terminals, difference output means connected to said first and second conduction paths, and means for supplying constant current connected to said first and second conduction paths; and waveform generation means connected to said first and second conduction paths for selectively operating one of said first and second means when a voltage applied to said common input terminal is within one of a plurality of predetermined intervals of voltage.
Claim 3
Dependent Claim
62 words
An analog-to-digital converter in accordance with claim 1 wherein said waveform generation means comprises means for connecting said waveform generation means to apply a plurality of predetermined waveform pairs in sequence to said first and second conduction paths, first and second waveforms of each of said plurality of predetermined waveform pairs being synchronously applied to said first and second conduction paths, respectively.
Claim 4
Dependent Claim
61 words
An analog-to-digital converter in accordance with claim 1 herein said first and second means comprise respectively first and second transistors whose individual collector and emitter electrodes are connected respectively in parallel with said first and second impedance means; and wherein said first and second input voltage terminals are individually connected to the respective base electrodes of said first and second transistors.
Claim 5
Dependent Claim
23 words
An analog-to-digital converter in accordance with claim 3 wherein said output means comprises a difference circuit connected to collector terminals of said transistors.
Claim 6
Dependent Claim
31 words
An analog-to-digital converter in accordance with claim 3 wherein said waveform generation means comprises first and second waveform generators connected to the emitter terminals respectively of said first and second transistors.
Claim 7
Dependent Claim
41 words
An analog-to-digital converter in accordance with claim 3, wherein said waveform generation means comprises a waveform generator having an output connected to said first conduction path, and a resistor, said resistor being connected between said output and said second conduction path.
Claim 8
Dependent Claim
45 words
An analog-to-digital converter in accordance with claim 1 wherein said waveform generation means includes means to apply one constant voltage waveform pair defining a voltage interval to said first and second conduction paths during each time interval of voltage application to said common input terminal.
Claim 9
Dependent Claim
34 words
A multibit analog-to-digital converter comprising a plurality of decision circuits individually comprising first and second conduction paths, first and second transistors connected respectively in said first and second conduction paths, through the collector and
Claim 10
Dependent Claim
34 words
A multibit analog-to-digital converter comprising a plurality of decision circuits individually comprising first and second conduction paths, first and second transistors connected respectively in said first and second conduction paths, through the collector and
Claim 11
Dependent Claim
36 words
An analog-to-digital converter in accordance with claim 7 wherein said waveform generators for at least one decision circuit generate one predetermined interval of voltage with respect to the reference voltage level during each sampling time interval.
Claim 12
Dependent Claim
67 words
An analog-to-digital converter in accordance with claim 7 wherein said waveform generators for at least one decision circuit comprise a means for generating a sequential plurality of predetermined intervals of voltage with respect to the input voltage reference level during each sampling time interval, and where the first and second voltage waveforms defining each voltage interval are synchronously coupled to the first and second conduction paths, respectively.
Claim 13
Dependent Claim
40 words
An analog-to-digital converter in accordance with claim 7 wherein said waveform generators include means defining said predetermined intervals of voltage to provide a coded binary representation of the input voltage magnitude directly from outputs of said difference output means, collectively.
Claim 14
Dependent Claim
136 words
An analog-to-digital converter including a decision circuit comprising first and second transistors connected respectively in first and second conduction paths through the collector and emitter terminals of said transistors, first and second resistors connected in parallel respectively with said first and second transistors, means for supplying constant current to said paths, difference output means connected to said paths, and an input terminal connected in common to the base terminals of said transistors; sampling means connected to said input terminal; means for generating a plurality of predetermined waveform pairs, means for connecting said waveform generating means to apply said plurality of predetermined waveform pairs in sequence to said first and second conduction paths, first and second waveforms of each of said plurality of predetermined waveform pairs being synchronously applied to said first and second conduction paths respectively.
Claim 15
Dependent Claim
136 words
An analog-to-digital converter including a decision circuit comprising first and second transistors connected respectively in first and second conduction paths through the collector and emitter terminals of said transistors, first and second resistors connected in parallel respectively with said first and second transistors, means for supplying constant current to said paths, difference output means connected to said paths, and an input terminal connected in common to the base terminals of said transistors; sampling means connected to said input terminal; means for generating a plurality of predetermined waveform pairs, means for connecting said waveform generating means to apply said plurality of predetermined waveform pairs in sequence to said first and second conduction paths, first and second waveforms of each of said plurality of predetermined waveform pairs being synchronously applied to said first and second conduction paths respectively.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-06-14 | 1974-12-14 | 1975-06-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-06-14 | 1978-12-14 | 1979-06-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-06-14 | 1982-12-14 | 1983-06-15 | $7700.00 | Window Closed / Lapsed |