Method and apparatus for decoding binary digital signals

Claim 1

Apparatus for decoding a recorded or transmitted analog signal representing a stream of bits wherein a signal transition occurring at the center of a bit is decoded as a binary ''''1'''' or ''''0'''' depending upon the direction of the transition, said apparatus comprising: a. a phase lock loop capable of locking onto a multiple of the bit frequency of the incoming stream of bits, said loop having a first output at a preselected multiple of said bit frequency and a second output defining the beginning and end of each bit; b. a counter capable of operating at a preselected multiple of said bit frequency as determined by said first output; c. means acting responsive to said second output for presetting said counter at the beginning of each bit; and d. logic circuit means receiving said analog signal and both said first and second loop outputs, said logic circuit means causing said counter to operate responsive to said first output in a mode which depends upon the level of the analog signal and the instantaneous position of the signal within said bit as determined by said second output, said logic circuit including means examining the contents of said counter at the end of each bit cell as determined by said second output for determining the binary value of said bit.

Claim 9

A method for decoding an analog signal representing a stream of bits wherein the binary value of each bit is determined by the direction of the signal transition at the center of the bit, said method comprising the steps of: a. generating a first signal at some frequency which is a multiple of the bit frequency; b. generating a second signal defining the beginning, center and end of each bit; c. operating a counter responsive to said first signal and in a mode which depends upon the level of the analog signal and the instantaneous position of said analog signal within said bit as defined by said second output; and d. reading said counter at the end of each bit as defined by said second signal and assigning a binary one or zero value to said bit depending upon whether the contents of said counter is above or below a predetermined number.

Claim 10

A method for decoding an analog signal representing a stream of bits wherein the binary value of each bit is determined by the direction of the signal transition at the center of the bit, said method comprising the steps of: a. generating a first signal at some frequency which is a multiple of the bit frequency; b. generating a second signal defining the beginning, center and end of each bit; c. operating a counter responsive to said first signal and in a mode which depends upon the level of the analog signal and the instantaneous position of said analog signal within said bit as defined by said second output; and d. reading said counter at the end of each bit as defined by said second signal and assigning a binary one or zero value to said bit depending upon whether the contents of said counter is above or below a predetermined number.