US3761809A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Noise modulated analogue signal presence detector
Assignee: United States Department of the Navy
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Filing: 1970-04-27
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Granted: 1973-09-25
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Expires: 1990-04-27
Abstract
Abstract A circuit for detecting presence of an analogue signal of unknown frequency in a noise environment. Detection is accomplished by determining and comparing the time variation between successive trailing edge zero crossings of the received signal. The components are a bandpass filter for passing only the frequency bandwidth within which the analogue signal is thought to be; an analogue to digital conversion means which produces a pulse everytime a trailing edge zero crossing occurs; an up-down counter, phase window detector, and frequency window detector which together determine and compare the time variation between successive trailing edge zero crossings and make a signal present or signal not present decision; and a post decision averaging means for averaging the signal present decisions received over a period of time, for providing greater protection against false detection.
Inventors
- 👤 J Lockitt
- 👤 T Eller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 18:34
CPC Classifications
G; G01; G01R; G01R23/00; Y; Y10; Y10S; Y10S367/00; Y10S367/901
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
265 words
A signal detector system comprising: means for generating a first control pulse at a first output in response to a first trailing edge zero crossing of a received signal, generating a second control pulse at a second output in response to a second trailing edge zero crossing of the received signal, and a third control pulse at said first output in response to a third trailing edge zero crossing of the received signal; clock pulse generating means; an up-down counter having a count up mode and a count down mode connected to said clock pulse generating means for counting said clock pulse and connected to said control pulse generating means, said counter being responsive to the first control pulse to initiate its count up mode, responsive to the second control pulse to terminate its count up mode and initiate its count down mode, and responsive to the third control pulse to terminate its count down mode, one complete cycle of the counter consisting of a count up mode and a count down mode; a phase window detector connected to said up-down counter, and responsive to said counter completing a cycle, to make a signal present or signal not-present decision, based on the residual count of said counter; a frequency window detector connected to said up-down counter, and responsive to said counter terminating its count up mode, to make a frequency decision on the incoming signal; and an AND gate connected to said phase window detector and said frequency window detector, and responsive to the decisions from both said detectors to produce a signal presence signal.
Claim 2
Dependent Claim
265 words
A signal detector system comprising: means for generating a first control pulse at a first output in response to a first trailing edge zero crossing of a received signal, generating a second control pulse at a second output in response to a second trailing edge zero crossing of the received signal, and a third control pulse at said first output in response to a third trailing edge zero crossing of the received signal; clock pulse generating means; an up-down counter having a count up mode and a count down mode connected to said clock pulse generating means for counting said clock pulse and connected to said control pulse generating means, said counter being responsive to the first control pulse to initiate its count up mode, responsive to the second control pulse to terminate its count up mode and initiate its count down mode, and responsive to the third control pulse to terminate its count down mode, one complete cycle of the counter consisting of a count up mode and a count down mode; a phase window detector connected to said up-down counter, and responsive to said counter completing a cycle, to make a signal present or signal not-present decision, based on the residual count of said counter; a frequency window detector connected to said up-down counter, and responsive to said counter terminating its count up mode, to make a frequency decision on the incoming signal; and an AND gate connected to said phase window detector and said frequency window detector, and responsive to the decisions from both said detectors to produce a signal presence signal.
Claim 3
Dependent Claim
18 words
The detector system of claim 1 further comprising a bandpass filter connected to the input of said means.
Claim 4
Dependent Claim
67 words
The detector system of claim 1 further comprising: a shift register connected to the output of said AND gate for receiving and storing an n number of signal presence signals from said AND gate; and an m out of n detector connected to said shift register, and responsive to an m number of signal presence signals in said shift register, to produce a final signal present decision.
Claim 5
Dependent Claim
18 words
The detector system of claim 3 further comprising a bandpass filter connected to the input of said means.
Claim 6
Dependent Claim
89 words
The signal detector system of claim 1 wherein said means comprises: a limiter for producing a pulse for each trailing edge zero crossing of the signal at its input; and a control flip-flop having first and second outputs and an input connected to said limiter, being responsive to the pulses at its input to place a control pulse at the first output in response to a first pulse at its input and place a control pulse at its second output in response to a second pulse at its input.
Claim 7
Dependent Claim
66 words
The detector system of claim 5 further comprising: a shift register connected to the output of said AND gate for receiving and storiNg an n number of signal presence signals from said AND gate; and an m out of n detector connected to said shift register and responsive to an m number of signal presence signals in said register to produce a final signal present decision.
Claim 8
Dependent Claim
27 words
The detector system of claim 5 further comprising a bandpass filter connected to the input of said limiter for limiting the frequency bandwidth of the signal received.
Claim 9
Dependent Claim
66 words
The detector system of claim 7 further comprising: a shift register connected to the output of said AND gate for receiving and storing an n number of signal presence signals from said AND gate; and an m out of n detector connected to said shift register and responsive to an m number of signal presence signals in said register to produce a final signal present decision.
References Cited (Backward Citations)
US3317828A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-09-24 | 1977-03-26 | 1977-09-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-09-24 | 1981-03-26 | 1981-09-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-09-24 | 1985-03-26 | 1985-09-25 | $7700.00 | Window Closed / Lapsed |