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US3853402A
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Digital gated depth of field intensity equalizer
Assignee: United States Department of the Army
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Filing: 1974-02-01
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Granted: 1974-12-10
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Expires: 1994-02-01
Abstract
Abstract A digital gating system for an image intensifier that has a built in read only memory weighted to duty cycle the power supply of an image intensifier in accordance with the inverse square law for returned illumination. A pulsing illuminator, which is generally an integral part of the image intensifier system, projects a train of illumination pulses outward which strikes targets and is reflected and returned to the image intensifier. Returned illumination from these targets is reduced according to the inverse square law. The present invention discloses a digital method of controlling a programmed read only memory that switches an image intensifier ''''on'''' more often in time as each illumination pulse travels through both the distances to and return from targets at increasing distances away from the image intensifier. Reflections from close targets are looked at less often by the image intensifier than reflections from targets at the maximum range. The number of looks, or activations, of the image intensifier are weighted commensurate with the inverse square law.
Inventors
- 👤 D Nichols
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 03:36
CPC Classifications
G; G01; G01S; G01S17/00; G01S17/88; G01S17/89; G01S17/02; G01S17/06; G01S17/08; G01S17/10; G01S17/18
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
424 words
A digital gating system for an image intensifier in which the image intensifier is gated on in accordance with the inverse square law in range, the system comprising: a pulsed illuminator source producing output trigger pulses therefrom; a switching circuit having a first and a second input and a first and a second output therefrom with first of said inputs being connected to and operating simultaneously with said pulsed illuminator; a pulsing circuit having an input connected to said first output from said switching circuit; a four stage binary counter having a first and a second input and four outputs therefrom; an address counter having an input connected to said second output from said switching circuit and having multiple outputs therefrom; a read only memory having multiple inputs that are connected to said multiple outputs from said address counter and having four outputs therefrom, said read only memory having stored therein an assigned number of switching pulses in a total cycle of sixty four switching pulses at each delay on said multiple outputs from said address counter to the input of said read only memory; a four bit binary comparator having four inputs from said read only memory and four inputs from said four stage binary counter and two outputs therefrom; a logic circuit having three inputs from three of said four outputs from said four stage binary counter and having an output therefrom; and gates switches and power supply having a first and a second input and an output therefrom wherein said output from said logic circuit produce a trailing edge pulse when said four stage binary counter has cycled through all four outputs wherein said trailing edge pulse is simultaneously applied to said first input of said gated switches and power supply and to said second input of said switching circuit for stopping said switching circuit and to said four stage binary counter for resetting said four stage binary to receive the next output trigger pulse from said pulsed illuminator source for triggering said switching and pulsing circuits and wherein said output from said four bit binary comparator produces a leading edge that is applied to said second input to said gated switches and power supply whereby said leading edge is varied in time commensurate with the inverse square law of returned illumination and said leading edge activates switches within said gated switches and power supply that applies said power supply to an image intensifier tube and said trailing edge deactivates said switches to remove said power supply from said image intensifier.
Claim 2
Dependent Claim
424 words
A digital gating system for an image intensifier in which the image intensifier is gated on in accordance with the inverse square law in range, the system comprising: a pulsed illuminator source producing output trigger pulses therefrom; a switching circuit having a first and a second input and a first and a second output therefrom with first of said inputs being connected to and operating simultaneously with said pulsed illuminator; a pulsing circuit having an input connected to said first output from said switching circuit; a four stage binary counter having a first and a second input and four outputs therefrom; an address counter having an input connected to said second output from said switching circuit and having multiple outputs therefrom; a read only memory having multiple inputs that are connected to said multiple outputs from said address counter and having four outputs therefrom, said read only memory having stored therein an assigned number of switching pulses in a total cycle of sixty four switching pulses at each delay on said multiple outputs from said address counter to the input of said read only memory; a four bit binary comparator having four inputs from said read only memory and four inputs from said four stage binary counter and two outputs therefrom; a logic circuit having three inputs from three of said four outputs from said four stage binary counter and having an output therefrom; and gates switches and power supply having a first and a second input and an output therefrom wherein said output from said logic circuit produce a trailing edge pulse when said four stage binary counter has cycled through all four outputs wherein said trailing edge pulse is simultaneously applied to said first input of said gated switches and power supply and to said second input of said switching circuit for stopping said switching circuit and to said four stage binary counter for resetting said four stage binary to receive the next output trigger pulse from said pulsed illuminator source for triggering said switching and pulsing circuits and wherein said output from said four bit binary comparator produces a leading edge that is applied to said second input to said gated switches and power supply whereby said leading edge is varied in time commensurate with the inverse square law of returned illumination and said leading edge activates switches within said gated switches and power supply that applies said power supply to an image intensifier tube and said trailing edge deactivates said switches to remove said power supply from said image intensifier.
Claim 3
Dependent Claim
96 words
A digital gating system as set forth in claim 1 wherein said address counter has six outputs with five of said outputs applied directly to said read only memory to apply bInary counts thereto and said sixth output is applied directly to four of eight outputs from said read only memory and through an inverter to the other four of said eight outputs for producing a total 64 word and 4 bit outputs from said read only memory in which a programmed number of the 64 words are used at each binary count delay representing range.
Claim 4
Dependent Claim
32 words
A digital gating system as set forth in claim 2 wherein said binary count delay representing range is a total of nine delays through the entire useable range of the image intensifier.
Claim 5
Dependent Claim
32 words
A digital gating system as set forth in claim 2 wherein said binary count delay representing range is a total of ten delays through the entire useable range of the image intensifier.
Claim 6
Dependent Claim
126 words
A digital gating system as set forth in claim 3 wherein read only memory comprises steering logic having eight outputs connected to first inputs of eight NAND logic circuits in parallel with the first four of said eight NAND logic circuits having a second input thereto directly from said sixth input from said address counter and the second four of said eight NAND logic circuits having a second input thereto which is an inverted said sixth output from said address counter wherein the four outputs from each of said first and second four NAND logic circuits are respectively cross connected as first and second inputs to a third four NAND logic circuits providing said 64 word and 4 bit output therefrom to said four binary comparator.
Claim 7
Dependent Claim
112 words
A digital gating system as set forth in claim 5 wherein said two outputs from said comparator have either a high voltage on one of said outputs or a low voltage on the other of said outputs in which the two outputs are applied to an NAND logic circuit that produces multiple output leading edge pulses according to the time lapsed with respect to the inverse square law from each illumination pulse wherein the multiple output leading edge pulses switch on said gate switches and power supply for providing power to the image intensifier over a longer period of time as the time lapse increases from the time of the illumination pulse.
Claim 8
Dependent Claim
81 words
A digital gating system as set forth in claim 6 wherein said read only memory further comprises a complimentary output digi-switch having four binary outputs therefrom that are sequentially connected to said third four NAND logic circuits and is serially connected to an NAND logic circuit and inverter as a third input to all of said first and second four of said eight NAND logic circuits to allow for selection of a single range by selecting the output of said digi-switch.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-12-09 | 1978-06-10 | 1978-12-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-12-09 | 1982-06-10 | 1982-12-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-12-09 | 1986-06-10 | 1986-12-10 | $7700.00 | Window Closed / Lapsed |