Patent US2270881A successfully refreshed from Google Patents.
US3852623A
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US
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Timing circuit
Assignee: Motors Liquidation Co
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Filing: 1973-07-12
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Granted: 1974-12-03
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Expires: 1993-07-12
Abstract
Abstract A timing circuit for energizing an output line a predetermined time after energization of a start of input line. The timer charges a capacitor through an FET operating in a self-biased mode so that current flow is constant and voltage rise is linear with time. The potential of the capacitor is applied to the gate of a second FET, the drain of which is connected to ground through a controlled voltage circuit. When the capacitor voltage reaches a sufficiently high level, the second FET conducts and energizes a transistor which supplies the output circuit. The timer also includes a reset switch which may be closed to discharge the capacitor.
Inventors
- 👤 R Nelson
- 👤 O Watts
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 23:00
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/28; F; F02; F02C; F02C7/00; F02C7/26; F05; F05D; F05D2270/00; F05D2270/30; F05D2270/301
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
156 words
A timing circuit comprising, in combination, a first FET having its source connected to an input signal line; a resistor and a capacitor connected in series between the drain of the FET and a source of datum potential; a second FEt, the gates of both FET''s being connected to The junction between the resistor and capacitor, so that the capacitor is charged by a constant controlled current and the potential on the gate of the second FET rises linearly with time when the signal line is energized; a second resistor connecting the source of the second FET to the input signal line; a source of constant potential intermediate the signal and datum potentials connected to the drain of the second FET; and an output line connected to the junction between the second resistor and the source of the second FET, the second FET energizing the output line at a predetermined level of charge on the capacitor.
Claim 2
Dependent Claim
156 words
A timing circuit comprising, in combination, a first FET having its source connected to an input signal line; a resistor and a capacitor connected in series between the drain of the FET and a source of datum potential; a second FEt, the gates of both FET''s being connected to The junction between the resistor and capacitor, so that the capacitor is charged by a constant controlled current and the potential on the gate of the second FET rises linearly with time when the signal line is energized; a second resistor connecting the source of the second FET to the input signal line; a source of constant potential intermediate the signal and datum potentials connected to the drain of the second FET; and an output line connected to the junction between the second resistor and the source of the second FET, the second FET energizing the output line at a predetermined level of charge on the capacitor.
Claim 3
Dependent Claim
166 words
A timing circuit comprising, in combination, a first FET having its source connected to an input signal line; a resistor and a capacitor connected in series between the drain of the FET and a source of datum potential; a second FET, the gates of both FET''s being connected to the junction between the resistor and capacitor, so that the capacitor is charged by a constant controlled current and the potential on the gate of the second FET rises linearly with time when the signal line is energized; a second resistor connecting the source of the second FET to the input signal line; a source of constant potential intermediate the signal and datum potentials comprising a constant-voltage-drop transistor circuit connected between the datum potential source and the drain of the second FET; and an output line connected to the junction between the second resistor and the source of the second FET, the second FET energizing the output line at a predetermined level of charge on the capacitor.
Claim 4
Dependent Claim
166 words
A timing circuit comprising, in combination, a first FET having its source connected to an input signal line; a resistor and a capacitor connected in series between the drain of the FET and a source of datum potential; a second FET, the gates of both FET''s being connected to the junction between the resistor and capacitor, so that the capacitor is charged by a constant controlled current and the potential on the gate of the second FET rises linearly with time when the signal line is energized; a second resistor connecting the source of the second FET to the input signal line; a source of constant potential intermediate the signal and datum potentials comprising a constant-voltage-drop transistor circuit connected between the datum potential source and the drain of the second FET; and an output line connected to the junction between the second resistor and the source of the second FET, the second FET energizing the output line at a predetermined level of charge on the capacitor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-12-02 | 1978-06-03 | 1978-12-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-12-02 | 1982-06-03 | 1982-12-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-12-02 | 1986-06-03 | 1986-12-03 | $7700.00 | Window Closed / Lapsed |