US3842405A
Expired / Lapsed
US
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Communications control unit
Assignee: International Business Machines Corp
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Filing: 1972-02-15
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Granted: 1974-10-15
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Expires: 1992-02-15
Abstract
Abstract A communications control unit, integrated into a processor, enables lines and modems to be changed or replaced by different types of lines and modems without changing the control unit hardware. A common modem adapter design can be used in the control unit for different data rates. A processor microprogram and a simple control unit local microprogram (dynamically changeable during the transfer of data) obviate the need for different adapters for each line and modem type. Both microprograms cooperate to control data transfer.
Inventors
- 👤 B Key
- 👤 M Hockings
- 👤 J Stredwick
- 👤 M Lovelace
- 👤 H Rankin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 17:59
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/382; G06F13/385
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
320 words
In a data processing system having a plurality of communication lines interconnecting a central processor with different types of terminals by way of modems terminating both ends of each line and means within the processor producing signals for controlling data transfer between the processor and the terminals, an integrated control unit comprising a plurality of similar adapters having means for storing tags, each adapter coupling a respective one of the lines to the control unit, a store storing a group of microinstructions for each line, each group including control, timing and data service instructions for respectively monitoring lines for incoming data and control signals, synchronizing the control unit with line data rates, and controlling data transfers between the lines and the store, each timing instruction having an initial count value which is a function of the rate at which data is transmitted over its line, means for periodically accessing the microinstructions in sequence, means responsive to a processor request for data transfer over one of the lines for modifying the logical state of a bit in a first control instruction in the group corresponding to the one line after the latter instruction is accessed, thereby indicating the line to be active for transmitting data thereover, means responsive to the modified instruction when it is thereafter accessed for permitting execution of succeeding control and timing instructions in the corresponding group each time they are subsequently accessed, means thereafter effective upon execution of the timing instructions of the corresponding group a predetermined number of times determined by the initial count values for executing a succeeding data service instruction in the corresponding group to transfer data between said one line and a location in the store holding a data field of the data service instruction, and means responsive to the processor signals for transferring data between the processor and the location in the store holding the data field of the data service instruction.
Claim 2
Dependent Claim
320 words
In a data processing system having a plurality of communication lines interconnecting a central processor with different types of terminals by way of modems terminating both ends of each line and means within the processor producing signals for controlling data transfer between the processor and the terminals, an integrated control unit comprising a plurality of similar adapters having means for storing tags, each adapter coupling a respective one of the lines to the control unit, a store storing a group of microinstructions for each line, each group including control, timing and data service instructions for respectively monitoring lines for incoming data and control signals, synchronizing the control unit with line data rates, and controlling data transfers between the lines and the store, each timing instruction having an initial count value which is a function of the rate at which data is transmitted over its line, means for periodically accessing the microinstructions in sequence, means responsive to a processor request for data transfer over one of the lines for modifying the logical state of a bit in a first control instruction in the group corresponding to the one line after the latter instruction is accessed, thereby indicating the line to be active for transmitting data thereover, means responsive to the modified instruction when it is thereafter accessed for permitting execution of succeeding control and timing instructions in the corresponding group each time they are subsequently accessed, means thereafter effective upon execution of the timing instructions of the corresponding group a predetermined number of times determined by the initial count values for executing a succeeding data service instruction in the corresponding group to transfer data between said one line and a location in the store holding a data field of the data service instruction, and means responsive to the processor signals for transferring data between the processor and the location in the store holding the data field of the data service instruction.
Claim 3
Dependent Claim
403 words
In a data processing system having a plurality of communication lines interconnecting a central processor with different types of terminals by way of modems terminating both ends of each line, and having microprogram instruction storage and control means integral with the processor for controlling the modems and terminals for transfer of information between the processor and terminals, in combination with said lines and processor, a data transfer control means comprising a local storage means for storing local microinstruction sets for each line; means including a source of periodic signals for periodically accessing the microinstructions one at a time in sequence; the sets including in order control microinstructions, timing microinstructions having initial count values therein which are a function of the data rates on their lines, and data service microinstructions having fields for storing data to be transferred between the processor and a respective terminal; local store microinstruction responsive means including an arithmetic and logical unit, an active latch, means responsive to local store microinstructions in each set for controlling the set and reset states of the latch, and means responsive to the set and reset states of the latch for rendering the arithmetic and logic unit effective to respectively permit and inhibit the execution of succeeding microinstructions in the set; means responsive to processor signals for transferring data between the processor and local store locations storing data service microinstructions; said local store microinstruction responsive means responsive to signals produced by each data service microinstruction when accessed after the active latch is set by a next preceding microinstruction for transferring data between the location storing the data service microinstruction and the modem terminating the Line corresponding to the set; said local store microinstruction responsive means responsive to local control microinstructions during said periodic accessing for setting the latch to control the rate of data transfer between the modems and locations storing respective data service microinstructions by monitoring respective modem clocked lines to set the latch when a modem clock signal appears on the respective line; and said local store microinstruction responsive means responsive to local timing microinstructions during said periodic accessing for setting the latch to control the rate of data transfer between the modems and locations storing respective data service microinstructions by sequentially updating count values in the timing microinstructions, once for each periodic access, from their initial values to a predetermined value to set the latch when said predetermined value is reached.
Claim 4
Dependent Claim
403 words
In a data processing system having a plurality of communication lines interconnecting a central processor with different types of terminals by way of modems terminating both ends of each line, and having microprogram instruction storage and control means integral with the processor for controlling the modems and terminals for transfer of information between the processor and terminals, in combination with said lines and processor, a data transfer control means comprising a local storage means for storing local microinstruction sets for each line; means including a source of periodic signals for periodically accessing the microinstructions one at a time in sequence; the sets including in order control microinstructions, timing microinstructions having initial count values therein which are a function of the data rates on their lines, and data service microinstructions having fields for storing data to be transferred between the processor and a respective terminal; local store microinstruction responsive means including an arithmetic and logical unit, an active latch, means responsive to local store microinstructions in each set for controlling the set and reset states of the latch, and means responsive to the set and reset states of the latch for rendering the arithmetic and logic unit effective to respectively permit and inhibit the execution of succeeding microinstructions in the set; means responsive to processor signals for transferring data between the processor and local store locations storing data service microinstructions; said local store microinstruction responsive means responsive to signals produced by each data service microinstruction when accessed after the active latch is set by a next preceding microinstruction for transferring data between the location storing the data service microinstruction and the modem terminating the Line corresponding to the set; said local store microinstruction responsive means responsive to local control microinstructions during said periodic accessing for setting the latch to control the rate of data transfer between the modems and locations storing respective data service microinstructions by monitoring respective modem clocked lines to set the latch when a modem clock signal appears on the respective line; and said local store microinstruction responsive means responsive to local timing microinstructions during said periodic accessing for setting the latch to control the rate of data transfer between the modems and locations storing respective data service microinstructions by sequentially updating count values in the timing microinstructions, once for each periodic access, from their initial values to a predetermined value to set the latch when said predetermined value is reached.
Claim 5
Independent Claim
313 words
A method of synchronizing the transfer of data between a central processor and communication lines by means of processor and modem clocked adapters which adapters are independent of data transfer rates, said method comprising the steps of connecting each line to the processor alternatively by a processor clocked or a modem clocked adapter, storing sets of microinstructions in a local store, one set for each line and its adapter, periodically accessing the microinstruction sets in the local store in sequence, each microinstruction including control indicia, and each microinstruction further including a field from a group including a line monitoring field, a count field having an initial count value and a data buffer field, assigning initial values to the count fields of timing microinstructions which initial values are a function of the data rates on lines corresponding to the microinstructions, said processor initiating data transfer requests, initializing a first control microinstruction in a desired microinstruction set by setting a status bit therein when it is accessed subsequent to one of said initiated data transfer requests, executing each subsequent timing microinstruction in an initialized local store microinstruction set of a processor clocked adapter as it is accessed to update the count by a selected value, synchronizing the processor clocked adapters with the accessing of the store by electrically sensing timing instruction count values during the execution of timing instructions to determine when the values have changed to a fixed second value and by thereafter executing a next succeeding data service instruction when it is subsequently accessed to transfer data between a respective line and a data buffer field of the service instruction, and synchronizing the modem clocked adapters with the accessing of the store by electrically sensing timing signals from the modem when control microinstructions of initialized sets are accessed and by executing succeeding data service microinstructions in initialized sets when they are thereafter accessed.
Claim 6
Independent Claim
313 words
A method of synchronizing the transfer of data between a central processor and communication lines by means of processor and modem clocked adapters which adapters are independent of data transfer rates, said method comprising the steps of connecting each line to the processor alternatively by a processor clocked or a modem clocked adapter, storing sets of microinstructions in a local store, one set for each line and its adapter, periodically accessing the microinstruction sets in the local store in sequence, each microinstruction including control indicia, and each microinstruction further including a field from a group including a line monitoring field, a count field having an initial count value and a data buffer field, assigning initial values to the count fields of timing microinstructions which initial values are a function of the data rates on lines corresponding to the microinstructions, said processor initiating data transfer requests, initializing a first control microinstruction in a desired microinstruction set by setting a status bit therein when it is accessed subsequent to one of said initiated data transfer requests, executing each subsequent timing microinstruction in an initialized local store microinstruction set of a processor clocked adapter as it is accessed to update the count by a selected value, synchronizing the processor clocked adapters with the accessing of the store by electrically sensing timing instruction count values during the execution of timing instructions to determine when the values have changed to a fixed second value and by thereafter executing a next succeeding data service instruction when it is subsequently accessed to transfer data between a respective line and a data buffer field of the service instruction, and synchronizing the modem clocked adapters with the accessing of the store by electrically sensing timing signals from the modem when control microinstructions of initialized sets are accessed and by executing succeeding data service microinstructions in initialized sets when they are thereafter accessed.
Claim 7
Independent Claim
305 words
A method of transferring data between a central processor and communication lines using similar adapters independent of data transfer rates, said method comprising the steps of periodically accessing from a local store a microinstruction set of separate control, count and data service microinstructions for each line in sequence, the timing microinstructions having in count fields thereof initial count values which are a function of the data rates on their respective lines, processor initializing a respective microinstruction set incident to each data transfer request by changing active status indicia in the control microinstruction of the set when it is accessed and by returning the microinstruction to the local store, setting an active latch with said status indicia each time that the control microinstruction of the initialized set is thereafter accessed, monitoring the respective line for a change in signal level each time that the control miCroinstruction of the initialized microinstruction set is accessed to maintain the latch set, said active latch signaling the execution of the timing microinstructions of the initialized set when they are accessed while the latch is maintained set, incrementing count values in count microinstructions each time they are executed, from the initial count values toward a selected second value, electrically detecting when the second value is reached during the execution of a count microinstruction, signaling the execution of data service microinstructions in the initialized set when accessed after the second count value is detected, transferring data between a data field of a data service microinstruction and the respective line under control of the data service microinstruction when the data service microinstruction is accessed and executed, issuing interrupt signals when control and data service microinstructions are accessed and executed, and transferring data between the processor and data fields of data service microinstructions under processor control incident to the issuance of an interrupt signal
Claim 8
Independent Claim
305 words
A method of transferring data between a central processor and communication lines using similar adapters independent of data transfer rates, said method comprising the steps of periodically accessing from a local store a microinstruction set of separate control, count and data service microinstructions for each line in sequence, the timing microinstructions having in count fields thereof initial count values which are a function of the data rates on their respective lines, processor initializing a respective microinstruction set incident to each data transfer request by changing active status indicia in the control microinstruction of the set when it is accessed and by returning the microinstruction to the local store, setting an active latch with said status indicia each time that the control microinstruction of the initialized set is thereafter accessed, monitoring the respective line for a change in signal level each time that the control miCroinstruction of the initialized microinstruction set is accessed to maintain the latch set, said active latch signaling the execution of the timing microinstructions of the initialized set when they are accessed while the latch is maintained set, incrementing count values in count microinstructions each time they are executed, from the initial count values toward a selected second value, electrically detecting when the second value is reached during the execution of a count microinstruction, signaling the execution of data service microinstructions in the initialized set when accessed after the second count value is detected, transferring data between a data field of a data service microinstruction and the respective line under control of the data service microinstruction when the data service microinstruction is accessed and executed, issuing interrupt signals when control and data service microinstructions are accessed and executed, and transferring data between the processor and data fields of data service microinstructions under processor control incident to the issuance of an interrupt signal
Claim 9
Dependent Claim
326 words
In a data processing system having a plurality of communication lines interconnecting a central processor with different types of terminals by way of modems terminating both ends of each line and means within the processor producing signals for controlling data transfer between the processor and the terminals, apparatus for generating a plurality of variable timeout intervals on a time-shared basis, for controlling said rate of data transfer, comprising, a local storage means for storing in sequence a plurality of sets of microinstruction words, there being one set for each timeout interval being generated, each set including at least one control microinstruction followed by a first timing microinstruction having an initialized count value stored in a field therein, means for executing the microinstructions, accessing means including an address register and an incrementer for reading out all of the microinstructions in sequence one at a time from the storage means into said executing means, a periodically recurring timing signal rendering the accessing means effective once for each timing signal to read out all of said microinstructions, means included in the executing means responsive to each timing microinstruction for updating the count value of the timing microinstruction when it is executed in the executing means, an active latch, decode logic responsive to the control microinstruction in a set for setting the latch to a selected state to indicate the initiation of one of said timeout intervals, said executing means permitting the execution of the first timing microinstruction in the set only if said latch is set to said selected state when the timing instruction is read into the executing means, means included in the executing means responsive to each timing microinstruction when it is executed for transferring its updated count value to the microinstruction field in the storage means, and means responsive to a predetermined updated count value in each timing microinstruction in the executing means for generating an output signal indicating the completion of said one timeout interval.
Claim 10
Dependent Claim
326 words
In a data processing system having a plurality of communication lines interconnecting a central processor with different types of terminals by way of modems terminating both ends of each line and means within the processor producing signals for controlling data transfer between the processor and the terminals, apparatus for generating a plurality of variable timeout intervals on a time-shared basis, for controlling said rate of data transfer, comprising, a local storage means for storing in sequence a plurality of sets of microinstruction words, there being one set for each timeout interval being generated, each set including at least one control microinstruction followed by a first timing microinstruction having an initialized count value stored in a field therein, means for executing the microinstructions, accessing means including an address register and an incrementer for reading out all of the microinstructions in sequence one at a time from the storage means into said executing means, a periodically recurring timing signal rendering the accessing means effective once for each timing signal to read out all of said microinstructions, means included in the executing means responsive to each timing microinstruction for updating the count value of the timing microinstruction when it is executed in the executing means, an active latch, decode logic responsive to the control microinstruction in a set for setting the latch to a selected state to indicate the initiation of one of said timeout intervals, said executing means permitting the execution of the first timing microinstruction in the set only if said latch is set to said selected state when the timing instruction is read into the executing means, means included in the executing means responsive to each timing microinstruction when it is executed for transferring its updated count value to the microinstruction field in the storage means, and means responsive to a predetermined updated count value in each timing microinstruction in the executing means for generating an output signal indicating the completion of said one timeout interval.
Claim 11
Dependent Claim
112 words
The apparatus of claim 5 further comprising a second timing microinstruction in the storage means following the first timing microinstruction in one of the sets, said second timing microinstruction having an initialized count value stored therein, means including said latch responsive to the timeout indicating output signal corresponding to the first timing microinstruction of the one set for permitting the execution of the second timing microinstruction when it is read into the executing means, thereby causing updating of its count value, said output signal generating means being responsive to a predetermined updated count value in the second timing microinstruction for geneRating an output signal indicating completion of one of said timeout intervals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-10-14 | 1978-04-15 | 1978-10-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-10-14 | 1982-04-15 | 1982-10-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-10-14 | 1986-04-15 | 1986-10-15 | $7700.00 | Window Closed / Lapsed |