Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
308 words
A multiplexing system, comprising: a programable computer including a central processing unit and a modifiable data storage memory separate from said central processing unit; a plurality of data input-output devices operative to transmit and receive data in binary coded form as a series of characters, at least certain of said devices having character configurations and data transfer rates which differ from other of the devices; and a multiplexer connected to the computer and to each of the input-output devices operative to control the flow of data between the computer and the input-output devices, said multiplexer including: a scanner having a first mode of operation wherein it sequentially makes connection with each of the input-output devices at a first, relatively high rate in synchronism with the operation of the computer, and a second mode of operation wherein it maintains its connection with one of said inputoutput devices; a plurality of clocks each having a different output rate which is a multiple of the data transfer rate of at least one of the input-output devices and is substantially lower than said first scanning rate; means associated with each input-output device operative to cause the scanner to switch from its first mode to its second mode upon the simultaneous occurrence of a pulse from the clock having the data rate which is a multiple of the data rate of that particular device, that particular device being connected to the scanner, and the occurrence of either data being transmitted by that input-output device or data loaded in the computer memory for transmission to that input-output device; and means for transferring data between the computer and a particular input-output device during at least certain of the times in which the scanner is in its second mode and the scanner is connected to that input-output device, said transferring means being connected to the scanner.
Claim 2
Dependent Claim
308 words
A multiplexing system, comprising: a programable computer including a central processing unit and a modifiable data storage memory separate from said central processing unit; a plurality of data input-output devices operative to transmit and receive data in binary coded form as a series of characters, at least certain of said devices having character configurations and data transfer rates which differ from other of the devices; and a multiplexer connected to the computer and to each of the input-output devices operative to control the flow of data between the computer and the input-output devices, said multiplexer including: a scanner having a first mode of operation wherein it sequentially makes connection with each of the input-output devices at a first, relatively high rate in synchronism with the operation of the computer, and a second mode of operation wherein it maintains its connection with one of said inputoutput devices; a plurality of clocks each having a different output rate which is a multiple of the data transfer rate of at least one of the input-output devices and is substantially lower than said first scanning rate; means associated with each input-output device operative to cause the scanner to switch from its first mode to its second mode upon the simultaneous occurrence of a pulse from the clock having the data rate which is a multiple of the data rate of that particular device, that particular device being connected to the scanner, and the occurrence of either data being transmitted by that input-output device or data loaded in the computer memory for transmission to that input-output device; and means for transferring data between the computer and a particular input-output device during at least certain of the times in which the scanner is in its second mode and the scanner is connected to that input-output device, said transferring means being connected to the scanner.
Claim 3
Dependent Claim
70 words
The multiplexer of claim 1 wherein the computer performs a sequence of operations under control of instructions stored in its memory and means are provided within the multiplexer to cause the multiplexer to interrupt said sequence while a transfer of data between the memory and the input-output devices is being accomplished, said interruptions occuring at such time as the scanner is switched from the first mode into its second mode.
Claim 4
Dependent Claim
118 words
The multiplexer of claim 1 wherein a register is associated with each input-output device and means are provided, within each register, operative upon the simultaneous occurrence of a scanner connection to a particular device, the occurrence of a pulse from the clock associated with such device and the existence of data to be transferred between such device and the memory, for modifying the contents of the register associated with such device, and wherein certain states of the register condition the transfer of data between the register and the memory so that such transfers only occur at selected occurrences of the simultaneous scanner connection, a pulse output from the associated clock, and the existence of data to be transferred.
Claim 5
Dependent Claim
74 words
The multiplexer of claim 1 wherein each input-output device has a data storage register associated therewith and all connections to such input-output device are made through such data storage register, and wherein said data storage register contains information which is a function of the data rate of the associated input-output device, said data being employed to identify the clock having a rate which is a multiple of the data rate of such input-output device.
Claim 6
Dependent Claim
50 words
The multiplexer of claim 4 wherein each data storage register includes a section containing information relating to the character format of its associated input-output device and the multiplexer includes means for modifying the data transfer between the computer memory and the input-output device based on the contents of such section.
Claim 7
Dependent Claim
91 words
The multiplexer of claim 1 wherein said modifiable data storage memory includes space for storing information received from each input-output device, space for storing information to be transferred to each input-output device, and space for data which is a function of the nature of the character format of each input-output device, and including means for transferring data between said memory sections and each input-output device in accordance with the contents of said memory which relates to the character format of the input-output device to or from which data is being transferred.
Claim 8
Dependent Claim
412 words
In a system including a programable computer having a memory storage section and a central processing unit which performs a sequence of operations under control of instructions stored in the memory, and a plurality of data input-output devices each having a data transfer rate substantially lower than the data acceptance and transmission rate of the computer, at least certain of the input-output devices having data rates and word formats which differ from those of other of the input-output devices, means for connecting all of the input-output devices to the computer so that it may service them on a time-shared basis, comprising: a multiplexer device; electrical connections between the multiplexer device and the computer memory, the computer central processing unit and each of the input-output devices; a plurality of line adapter data registers each having a transmit section, a receive section, one being associated with each input-output device and being connected between that device and the multiplexer; a scanner associated with the multiplexer operative to make sequential connection with each of the line adapter registers, and to make sequential connection with the receive and the transmit section within a line adapter register; first logic means contained within the multiplexer operative under control of signals from the computer central processing unit to start the scanning process, second logic means contained within the multiplexer operative to stop the scanning process, third logic means contained within the multiplexer operative to determine the condition of the scanning process, fourth logic means contained within the multiplexer operative to modify the state of the scanning process, fifth logic means contained within the multiplexer operative to determine the condition of a line adapter register connected to the scanner and sixth logic means contained within the multiplexer operative to modify the condition of a line adapter register connected to the scanner; a plurality of clocks contained within the multiplexer each being associated with a particular one of the line adapter units; and means, connected to the computer, for interrupting the normal sequence of performance of instructions by the computer upon the simultaneous occurrence of the scanner being connected to a particular section of the line adapter register, the occurrence of a pulse from a clock associated with that line adapter register, and the presence of information in the line adapter register indicative of either the fact that the associated input-output device is transmitting data or that data to be provided to that associated input-output device is contained within the computer memory.
Claim 9
Dependent Claim
412 words
In a system including a programable computer having a memory storage section and a central processing unit which performs a sequence of operations under control of instructions stored in the memory, and a plurality of data input-output devices each having a data transfer rate substantially lower than the data acceptance and transmission rate of the computer, at least certain of the input-output devices having data rates and word formats which differ from those of other of the input-output devices, means for connecting all of the input-output devices to the computer so that it may service them on a time-shared basis, comprising: a multiplexer device; electrical connections between the multiplexer device and the computer memory, the computer central processing unit and each of the input-output devices; a plurality of line adapter data registers each having a transmit section, a receive section, one being associated with each input-output device and being connected between that device and the multiplexer; a scanner associated with the multiplexer operative to make sequential connection with each of the line adapter registers, and to make sequential connection with the receive and the transmit section within a line adapter register; first logic means contained within the multiplexer operative under control of signals from the computer central processing unit to start the scanning process, second logic means contained within the multiplexer operative to stop the scanning process, third logic means contained within the multiplexer operative to determine the condition of the scanning process, fourth logic means contained within the multiplexer operative to modify the state of the scanning process, fifth logic means contained within the multiplexer operative to determine the condition of a line adapter register connected to the scanner and sixth logic means contained within the multiplexer operative to modify the condition of a line adapter register connected to the scanner; a plurality of clocks contained within the multiplexer each being associated with a particular one of the line adapter units; and means, connected to the computer, for interrupting the normal sequence of performance of instructions by the computer upon the simultaneous occurrence of the scanner being connected to a particular section of the line adapter register, the occurrence of a pulse from a clock associated with that line adapter register, and the presence of information in the line adapter register indicative of either the fact that the associated input-output device is transmitting data or that data to be provided to that associated input-output device is contained within the computer memory.
Claim 10
Dependent Claim
35 words
The system of claim 7 wherein each of the clocks has a regular pulse output rate equal to an odd integral multiple of the data rates of the input-output devices with which it is associated.