Patent US3840863A successfully refreshed from Google Patents.
US3840863A
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Dynamic storage hierarchy system
Assignee: International Business Machines Corp
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Filing: 1973-10-23
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Granted: 1974-10-08
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Expires: 1993-10-23
Abstract
Abstract A data processing system having a main storage-buffer memory hierarchy in which various congruence mapping class configurations are dynamically provided by utilizing a fixed format main storage-buffer array unit. A directory is provided which generates buffer slot addresses in response to the class address portion of a main storage address word. Various block sizes of data may be associatively mapped into predefined areas of a buffer array. A single integrated circuit chip containing both main memory and buffer arrays may be used to implement various congruence classes by the selective application of input signals provided by the main storage address and a hierarchy directory.
Inventors
- 👤 R Fuqua
- 👤 G Hasler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 17:46
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0864; G06F2212/00; G06F2212/60; G06F2212/601
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
236 words
In a data processing system including a first and second memory, wherein data is organized in said first memory in at least one data class and wherein each data class is composed of a number of blocks of data, each containing a plurality of bytes, each of said blocks of data being addressable in response to a first memory block address provided by said system, and wherein data is organized in said second memory in the same number of classes as in said first memory, each of said classes in said second memory composed of a smaller number of blocks of data than in said first memory, each block of data in said second memory being addressable in response to a second memory block address provided, at least partially, by a directory, means responsive to a byte address provided by said system for addressing individual bytes within a block of data in said second memory, means for transferring blocks of data between said first and second memories, and directory means for controlling the transfer of blocks of data and for providing at least a portion of said second memory block address, the improvement comprising: means for changing the number of classes in which data is organized in said memories, said means altering said portion of said second memory block address provided by said directory to provide accessing of all blocks of data in said second memory.
Claim 2
Dependent Claim
236 words
In a data processing system including a first and second memory, wherein data is organized in said first memory in at least one data class and wherein each data class is composed of a number of blocks of data, each containing a plurality of bytes, each of said blocks of data being addressable in response to a first memory block address provided by said system, and wherein data is organized in said second memory in the same number of classes as in said first memory, each of said classes in said second memory composed of a smaller number of blocks of data than in said first memory, each block of data in said second memory being addressable in response to a second memory block address provided, at least partially, by a directory, means responsive to a byte address provided by said system for addressing individual bytes within a block of data in said second memory, means for transferring blocks of data between said first and second memories, and directory means for controlling the transfer of blocks of data and for providing at least a portion of said second memory block address, the improvement comprising: means for changing the number of classes in which data is organized in said memories, said means altering said portion of said second memory block address provided by said directory to provide accessing of all blocks of data in said second memory.
Claim 3
Dependent Claim
29 words
A data processing system set forth in claim 1 wherein said means for changing the number of classes is responsive to an initiallizing input signal provided by said system.
Claim 4
Dependent Claim
61 words
The data processing system set forth in claim 1 wherein said means for changing the number of classes increases the number of classes by a factor of 2n, where n is an integer greater than zero, by effecting the substitution of n address bits of the addresses provided by said system for n address bits in said second memory block address.
Claim 5
Dependent Claim
37 words
The data processing system set forth in claim 3 wherein the n address bits of the addresses provided by said system used to increase the number of classes are a part of said first memory block address.
Claim 6
Dependent Claim
35 words
The data processing system set forth in claim 3 wherein the n address bits of the addresses provided by said system used to increase the number of classes are a part of the byte address.
Claim 7
Dependent Claim
52 words
A memory hierarchy for a data processing system comprising: a large memory, a smaller memory, means for transferring blocks of data between said large and smaller memories, and means for selectively changing the number of locations in said small memory to which blocks of data in said large memory may be transferred.
Claim 8
Dependent Claim
52 words
A memory hierarchy for a data processing system comprising: a large memory, a smaller memory, means for transferring blocks of data between said large and smaller memories, and means for selectively changing the number of locations in said small memory to which blocks of data in said large memory may be transferred.
Claim 9
Dependent Claim
42 words
The memory hierarchy as set forth in claim 6 wherein said means for selectively changing the number of locations in said small memory to which blocks of data in said large memory may be transferred also changes the size of said blocks.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-10-07 | 1978-04-08 | 1978-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-10-07 | 1982-04-08 | 1982-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-10-07 | 1986-04-08 | 1986-10-08 | $7700.00 | Window Closed / Lapsed |