Patent US3840174A successfully refreshed from Google Patents.
US3840174A
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Precision digital interpolator
Assignee: RCA Corp
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Filing: 1973-05-29
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Granted: 1974-10-08
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Expires: 1993-05-29
Abstract
Abstract A clock signal of a first frequency is applied to a first binary counter. The first counter provides an output signal after counting to a predetermined binary number. The output signal causes a second clock signal, of a second frequency, to be applied to a second counter. The second counter provides a second output signal after counting to a binary number which is the complement of the predetermined binary number. The temporal position of the second output signal is varied, in steps equal to the difference in the periods of the two clocks, by varying the predetermined binary number.
Inventors
- 👤 R Craft
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 19:35
CPC Classifications
G; G01; G01S; G01S13/00; G01S13/66; G01S13/70; G06; G06F; G06F7/00; G06F7/60; G06F7/62
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
432 words
A digital interpolator comprising: first source of clock signals of a first given frequency; second source of clock signals of a second given frequency; first and second counters; wherein said first counter is responsive to said signals from said first clock source to provide a first output signal after a first predetermined number of clock signals has been counted in said first counter, said second counter is responsive to said signals from said second clock source for providing a second output signal after a second predetermined number of clock signals has been counted in said second counter, wherein the temporal position of said second output signal is a function of the difference in the periods of said clock signals and the relative values of said first and second predetermined numbers, and said first and second predetermined numbers are binary numbers, said second binary number being the complement of said first binary number; first input means coupling said first counter to said first clock source and responsive to a start signal for applying said clock signals from said first clock source to said first counter in response to said start signal, said input means comprising a first flip-flop having a set input, a reset input and an output, and a first logical AND gate having first and second inputs and an output, said set input being coupled to receive said start signal, said reset input being coupled to receive said second output signal and said output of said first flip-flop being coupled to said first input of said first gate, said first clock source being coupled to said second input of said first gate and said output of said first gate being coupled to said first counter; and second input means coupling said first counter to said second counter and responsive to said first output signal for applying said clock signals from said second clock source to said second countEr in response to said first output signal, said second input means comprising a second flip-flop having a set input, a reset input and an output, and a second logical AND gate having first and second inputs and an output, said set input of said second flip-flop being coupled to receive said first output signal, said reset input of said second flip-flop being coupled to receive said second output signal and said output of said second flip-flop being coupled to said first input of said second gate, said second clock source being coupled to said second input of said second gate, and said output of said second gate being coupled to said second counter.
Claim 2
Dependent Claim
432 words
A digital interpolator comprising: first source of clock signals of a first given frequency; second source of clock signals of a second given frequency; first and second counters; wherein said first counter is responsive to said signals from said first clock source to provide a first output signal after a first predetermined number of clock signals has been counted in said first counter, said second counter is responsive to said signals from said second clock source for providing a second output signal after a second predetermined number of clock signals has been counted in said second counter, wherein the temporal position of said second output signal is a function of the difference in the periods of said clock signals and the relative values of said first and second predetermined numbers, and said first and second predetermined numbers are binary numbers, said second binary number being the complement of said first binary number; first input means coupling said first counter to said first clock source and responsive to a start signal for applying said clock signals from said first clock source to said first counter in response to said start signal, said input means comprising a first flip-flop having a set input, a reset input and an output, and a first logical AND gate having first and second inputs and an output, said set input being coupled to receive said start signal, said reset input being coupled to receive said second output signal and said output of said first flip-flop being coupled to said first input of said first gate, said first clock source being coupled to said second input of said first gate and said output of said first gate being coupled to said first counter; and second input means coupling said first counter to said second counter and responsive to said first output signal for applying said clock signals from said second clock source to said second countEr in response to said first output signal, said second input means comprising a second flip-flop having a set input, a reset input and an output, and a second logical AND gate having first and second inputs and an output, said set input of said second flip-flop being coupled to receive said first output signal, said reset input of said second flip-flop being coupled to receive said second output signal and said output of said second flip-flop being coupled to said first input of said second gate, said second clock source being coupled to said second input of said second gate, and said output of said second gate being coupled to said second counter.
Claim 3
Dependent Claim
143 words
The combination comprising: first and second clock pulse means for producing pulses at different rates; first and second counter means, each for counting first and second certain numbers of pulses at an input means and producing an output signal in response to counting said certain numbers of pulses; first control means responsive to a control signal and said output signal from said second counter for coupling the pulses from the first clock means to the input means of said first counter during the time interval between said control signal and said output signal from the second counter; and second control means responsive to the output signals of said first and second counters for coupling the pulses from the second clock means to the input means of said second counter during the time interval between the output signals of said first and second counters.
Claim 4
Dependent Claim
143 words
The combination comprising: first and second clock pulse means for producing pulses at different rates; first and second counter means, each for counting first and second certain numbers of pulses at an input means and producing an output signal in response to counting said certain numbers of pulses; first control means responsive to a control signal and said output signal from said second counter for coupling the pulses from the first clock means to the input means of said first counter during the time interval between said control signal and said output signal from the second counter; and second control means responsive to the output signals of said first and second counters for coupling the pulses from the second clock means to the input means of said second counter during the time interval between the output signals of said first and second counters.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-10-07 | 1978-04-08 | 1978-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-10-07 | 1982-04-08 | 1982-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-10-07 | 1986-04-08 | 1986-10-08 | $7700.00 | Window Closed / Lapsed |