Digital word generating and receiving apparatus

Claim 2

A digital word generator for simultaneously producing time sequential bit patterns so as to provide at least two bits of parallel bit information in response to commands from a digital computer and adapted for use in connection therewith, comprising: at least two output terminals; at least two multibit local memories connected to the respective output terminals, each thereof being operable independently of the computer for receiving from a source and storing the bits of a digital signal pattern; a clock source producing a signal having a frequency related to the operation rate of the local memories; means for applying the clock signal to to said multibit memories to produce the bits of a digital signal pattern in time sequential relation simultaneously at each output terminal; and address means connectable to the computer and responsive to an address signal to render each of the local memories selectively operable in accordance with a parallel-bit word to be generated.

Claim 3

The digital word generator of claim 1, wherein the clock source is operable to produce clock signal pulses at variable frequencies in response to a command from the computer.

Claim 4

A digital word generator for producing digital bit patterns in response to commands from a digital computer and adapted for use in connection therewith, comprising: at least one output terminal; a multibit local memory connected to the output terminal and operable independently of the computer for receiving from the computer and storing the bits of a digital signal pattern; a clock source producing a signal having a frequency independent of the operational cycle time of the computer; means for applying the clock signal to the multibit memory to produce the bits of the digital signal pattern at the output terminal in time sequential relation; logic comparator means connectable to receive a digital signal from an external test point at one input thereto; means coupled to the local memory for applying the output thereof to the logic comparator means, the logic comparator means being operable to produce an error indication upon a discrepancy between the respective digital signals from the local memory and the test point; and an error memory connected to receive and store error indications from the logic comparator means.

Claim 5

A digital word generator for producing digital bit patterns in response to commands from a digital computer and adapted for use in connection therewith, comprising: at least one output terminal; a multibit local memory connected to the output terminal and operable independently of the computer for receiving from the computer and storing the bits of a digital signal pattern; a clock source producing a signal having a frequency independent of the operational cycle time of the computer; means for applying the clock signal to the multibit memory to produce the bits of the digital signal pattern at the output terminal in time sequential relation; logic comparator means connectable to receive a digital signal from an external test point at one input thereto; means coupled to the local memory for applying the output thereof to the logic comparator means, the logic comparator means being operable to produce an error indication upon a discrepancy between the respective digital signals from the local memory and the test point; and an error memory connected to receive and store error indications from the logic comparator means.

Claim 6

The digital word generator of claim 3 wherein the error memory comprises a register for sequentially storing the error indications at a rate corresponding to the rate of application of the bits of the digital word pattern from the local memory to the logic comparator means.

Claim 7

The digital word generator of claim 4, further comprising: means for producing a strobe signal for operating the error register at the bit application rate and in time displaced relation to the clock signal thereby to cause to be stored in the error memory only bits present at such displaced time.

Claim 8

The digital word generator of claim 5, wherein the time displacement of the strobe signal relative to the clock signal is variable.

Claim 9

A digital word generator for producing digital bit patterns in response to commands from a digital computer and adapted for use in connection herewith, comprising: at least two output terminals; at least two local multibit memories each comprised of a multistage register for sequentially storing bits of a digital word presented thereto in response to and at a rate determined by a clock signal; a clock source producing a signal having a frequency independent of the operational cycle time of the computer; and means for applying the clock signal to each of said multistage registers to produce simultaneously at said output terminals the bits of the respective digital signal patterns stored in said registers.

Claim 10

A digital word generator for producing digital bit patterns in response to commands from a digital computer and adapted for use in connection herewith, comprising: at least two output terminals; at least two local multibit memories each comprised of a multistage register for sequentially storing bits of a digital word presented thereto in response to and at a rate determined by a clock signal; a clock source producing a signal having a frequency independent of the operational cycle time of the computer; and means for applying the clock signal to each of said multistage registers to produce simultaneously at said output terminals the bits of the respective digital signal patterns stored in said registers.

Claim 11

The digital word generator of claim 7, wherein the register is operable to circulate the contents thereof, the gEnerator further comprising: bit storage means connected intermediate the output of the register and the output terminal and separately responsive to the clock signal for providing the stored bit to the output terminal irrespective of the presence of a signal bit at the register output.

Claim 12

A digital word generator for producing digital bit patterns in response to commands from a digital computer and adapted for use in connection therewith, comprising: at least one output terminal; a multibit local memory connected to the output terminal and operable independently of the computer for receiving from the computer and storing the bits of a digital signal pattern; a clock source producing a signal having a frequency independent of the operational cycle time of the computer; means for applying the clock signal to the multibit memory to produce the bits of the digital signal pattern at the output terminal in time sequential relation; logic comparator means connectable to receive a digital signal from an external test point at one input thereto; means coupled to the local memory for applying the output thereof to the logic comparator means, the logic comparator means being operable to produce an error indication upon a discrepancy between the respective digital signals from the local memory and the test point; and controllable switch means connected intermediate at least one of said output terminals and the test point, the switch means being responsive to a mode command from the computer for selectively connecting the test point to either the output terminal or the logic comparator.

Claim 13

A digital word generator for producing digital bit patterns in response to commands from a digital computer and adapted for use in connection therewith, comprising: at least one output terminal; a multibit local memory connected to the output terminal and operable independently of the computer for receiving from the computer and storing the bits of a digital signal pattern; a clock source producing a signal having a frequency independent of the operational cycle time of the computer; means for applying the clock signal to the multibit memory to produce the bits of the digital signal pattern at the output terminal in time sequential relation; logic comparator means connectable to receive a digital signal from an external test point at one input thereto; means coupled to the local memory for applying the output thereof to the logic comparator means, the logic comparator means being operable to produce an error indication upon a discrepancy between the respective digital signals from the local memory and the test point; and controllable switch means connected intermediate at least one of said output terminals and the test point, the switch means being responsive to a mode command from the computer for selectively connecting the test point to either the output terminal or the logic comparator.

Claim 14

A digital word generator for producing digital bit patterns in response to commands from a digital computer and adapted for use in connection therewith, comprising: at least one output terminal; a multibit local memory connected to the output terminal and operable independently of the computer for receiving from the computer and storing the bits of a digital signal pattern; a clock source producing a signal having a frequency related to the rate of serial production of bits at the output terminal; means for applying the clock signals to the multibit memory to produce the bits of the digital signal pattern at the output terminal in time sequential relation; logic comparator means connectable to receive a digital signal from an external test point at one input thereto; means coupled to the local memory for applying the output thereof to the logic comparator means, the logic comparator means being operable to produce an error indication upon a discrepancy between the respective digital signals from the local memory and the test point; and level sensitive means connected intermediate the test point and the logic comparator means and operable to provide an output signal to the latter only when the amplitude of the signal at the test point is embraced by predetermined amplitude levels.

Claim 15

A digital word generator for producing digital bit patterns in response to commands from a digital computer and adapted for use in connection therewith, comprising: at least one output terminal; a multibit local memory connected to the output terminal and operable independently of the computer for receiving from the computer and storing the bits of a digital signal pattern; a clock source producing a signal having a frequency related to the rate of serial production of bits at the output terminal; means for applying the clock signals to the multibit memory to produce the bits of the digital signal pattern at the output terminal in time sequential relation; logic comparator means connectable to receive a digital signal from an external test point at one input thereto; means coupled to the local memory for applying the output thereof to the logic comparator means, the logic comparator means being operable to produce an error indication upon a discrepancy between the respective digital signals from the local memory and the test point; and level sensitive means connected intermediate the test point and the logic comparator means and operable to provide an output signal to the latter only when the amplitude of the signal at the test point is embraced by predetermined amplitude levels.

Claim 16

The digital word generator of claim 10, further comprising: means responsive to a level command from the computer for developing at least one signal representing one of the predetermined amplitude levels, the level sensitive means being responsive to such level representative signal to establish controllably different predetermined levels.

Claim 17

A digital word generator for producing digital bit patterns in response to commands from a digital computer and adapted for use in connection therewith, comprising: at least one output terminal; a multibit local memory connected to the output terminal and operable independently of the computer for receiving from the computer and storing the bits of a digital signal pattern; a clock source producing a signal having a frequency related to the rate of production of serial bits at the output terminal; means for applying the clock signal to the multibit memory to produce the bits of the digital signal pattern at the output terminal in time sequential relation; MEANS responsive to a level command from the computer for generating a signal representing the desired amplitude level of the desired signals to be applied to the output terminals; and a level shifting circuit receiving the local memory output and responsive to the desired level-representative signal for producing at the output terminal a digital bit pattern having said desired amplitude level.

Claim 18

A digital word generator for producing digital bit patterns in response to commands from a digital computer and adapted for use in connection therewith, comprising: at least one output terminal; a multibit local memory connected to the output terminal and operable independently of the computer for receiving from the computer and storing the bits of a digital signal pattern; a clock source producing a signal having a frequency related to the rate of production of serial bits at the output terminal; means for applying the clock signal to the multibit memory to produce the bits of the digital signal pattern at the output terminal in time sequential relation; MEANS responsive to a level command from the computer for generating a signal representing the desired amplitude level of the desired signals to be applied to the output terminals; and a level shifting circuit receiving the local memory output and responsive to the desired level-representative signal for producing at the output terminal a digital bit pattern having said desired amplitude level.

Claim 19

In an automated diagnostic testing system for performing functional and dynamic testing of logic elements in a unit under test, the combination of: a digital computer providing selected command signals in accordance with a stored program; means for providing electrical test points for applying signals to and receiving signals from the unit under test; a digital word generator including plural storage registers for storing available digital bit patterns; a clock pulse generator for supplying to said storage registers, in response to a computer command, shift pulses to advance the stored digital bit patterns through the stages of the registers so that the bits in each of said patterns appear in mutually time displaced relation at the respective register outputs; means for applying the digital pattern bits at the register outputs to respective ones of the test points; a data reception channel associated with each of the storage registers, each reception channel including a comparator circuit having as inputs (a) the output of a respective register and (b) the input to the reception channel to develop an output signal representing discrepancies therebetween, and means responsive to a computer command for selectively connecting the test point to the reception channel input.

Claim 20

In an automated diagnostic testing system for performing functional and dynamic testing of logic elements in a unit under test, the combination of: a digital computer providing selected command signals in accordance with a stored program; means for providing electrical test points for applying signals to and receiving signals from the unit under test; a digital word generator including plural storage registers for storing available digital bit patterns; a clock pulse generator for supplying to said storage registers, in response to a computer command, shift pulses to advance the stored digital bit patterns through the stages of the registers so that the bits in each of said patterns appear in mutually time displaced relation at the respective register outputs; means for applying the digital pattern bits at the register outputs to respective ones of the test points; a data reception channel associated with each of the storage registers, each reception channel including a comparator circuit having as inputs (a) the output of a respective register and (b) the input to the reception channel to develop an output signal representing discrepancies therebetween, and means responsive to a computer command for selectively connecting the test point to the reception channel input.

Claim 21

The diagnostic testing system of claim 13, further comprising: an error storage register connected to receive the output signal developed by the comparator circuit; and means for applying a strobe signal to the error storage register in timed relationship with the clock pulse signal, thereby to store the comparator circuit output signal present at specific instants of time corresponding to times when a received signal is expected at the test point.

Claim 22

The diagnostic testing system of claim 14 further comprising: means jointly responsive to the signals at the outputs of the comparator circuits connected to respective test points to develop an error indication upon the occurrence of any discrepancy between the expected digital signal patterns and the digital signal patterns actually received at any test point.

Claim 23

The diagnostic testing system of claim 13, further comprising: address control means associated with each of the storage registers to develop a first command signal for enabling the storage registers associated with a test point which are addressed by the computer; and shift control means jointly responsive to the first command signal and to the shift pulses for storing the bits of the available digital bit pattern in the local storage register so addressed.

Claim 24

In an automated diagnostic testing system for performing functional and dynamic testing of logic elements in a unit under test, the combination of: a digital computer providing selected command signals in accordance with a stored program; means providing electrical test points for applying signals to and receiving signals from the unit under test; a digital word generator including at least one local storage register for storing available digital bit pattern information; a clock pulse signal generator for supplying to the storage register shift pulses to advance the stored digital bit pattern through the stages of the register so as to appear in mutually time displaced relation at the register output; means for controllably operating the local storage register so as to cause data at the output of said register to be recirculated to an input thereof, thereby to cause the stored digital bit pattern to be reentered thereinto In response to shift pulses; and means for applying the digital pattern bits at the register output to one of the test points.

Claim 25

In an automated diagnostic testing system for performing functional and dynamic testing of logic elements in a unit under test, the combination of: a digital computer providing selected command signals in accordance with a stored program; means providing electrical test points for applying signals to and receiving signals from the unit under test; a digital word generator including at least one local storage register for storing available digital bit pattern information; a clock pulse signal generator for supplying to the storage register shift pulses to advance the stored digital bit pattern through the stages of the register so as to appear in mutually time displaced relation at the register output; means for controllably operating the local storage register so as to cause data at the output of said register to be recirculated to an input thereof, thereby to cause the stored digital bit pattern to be reentered thereinto In response to shift pulses; and means for applying the digital pattern bits at the register output to one of the test points.

Claim 26

The diagnostic testing system of claim 17, wherein the applying means includes: data bit storage means connected to receive the local storage register output, said bit storage means having a gating input for receiving shift pulses and being operable to provide at an output thereof a digital bit representing the digital signal present at the local storage register output upon receipt of a shift pulse thereby.

Claim 27

In an automated diagnostic testing system for performing functional and dynamic testing of logic elements in a unit under test, the combination of: a digital computer providing selected command signals in accordance with with a stored program; means providing electrical test points for applying signals to and receiving signals from the unit under test; a digital word generator including at least one local storage register for storing available digital bit pattern information; a clock pulse signal generator for supplying to the storage register shift pulses to advance the stored digital bit pattern through the stages of the register so as to appear in mutually time displaced relation at the register output; means for applying the digital pattern bits at the register output to one of the test points; an index register having a bit storage capacity corresponding to the bit storage capacity of the local multibit register; means responsive to a computer command for storing at least one marker bit in the index register; and means responsive to the digital bit pattern received from the computer for locating the marker bit within the index register at a position representing the length of the stored digital bit pattern.

Claim 28

In an automated diagnostic testing system for performing functional and dynamic testing of logic elements in a unit under test, the combination of: a digital computer providing selected command signals in accordance with with a stored program; means providing electrical test points for applying signals to and receiving signals from the unit under test; a digital word generator including at least one local storage register for storing available digital bit pattern information; a clock pulse signal generator for supplying to the storage register shift pulses to advance the stored digital bit pattern through the stages of the register so as to appear in mutually time displaced relation at the register output; means for applying the digital pattern bits at the register output to one of the test points; an index register having a bit storage capacity corresponding to the bit storage capacity of the local multibit register; means responsive to a computer command for storing at least one marker bit in the index register; and means responsive to the digital bit pattern received from the computer for locating the marker bit within the index register at a position representing the length of the stored digital bit pattern.

Claim 29

The diagnostic testing system of claim 19, further comprising means responsive to a computer command for advancing he stored digntial bit pattern through the local multibit register and for simultaneously advancing the marker bit through the index register; and means responsive to the position for the marker bit for terminating advancement of the digital bit pattern upon arrival of the bits of such pattern at a desired position within the local multibit register.

Claim 30

A digital word checking apparatus for receiving and analyzing digital bit patterns and adapted for operation in response to commands from a digital computer, comprising: a multibit local memory operable independently of the computer for receiving from the computer and storing a digital bit pattern representing data expected to be received; a clock source producing a signal having a frequency related to the production of serial bit information at the memory output means responsive to a computer command signal for applying the clock source signal to the local memory to produce the bits of the digital pattern at the memory output in time sequential relation; logic comparator means jointly responsive to the bit pattern at the output of the local memory and the received signal for generating error bit indications upon any discrepancy between the expected and received bit patterns; and an error memory connected to receive and store error indications from the logic comparator means.

Claim 31

A digital word checking apparatus for receiving and analyzing digital bit patterns and adapted for operation in response to commands from a digital computer, comprising: a multibit local memory operable independently of the computer for receiving from the computer and storing a digital bit pattern representing data expected to be received; a clock source producing a signal having a frequency related to the production of serial bit information at the memory output means responsive to a computer command signal for applying the clock source signal to the local memory to produce the bits of the digital pattern at the memory output in time sequential relation; logic comparator means jointly responsive to the bit pattern at the output of the local memory and the received signal for generating error bit indications upon any discrepancy between the expected and received bit patterns; and an error memory connected to receive and store error indications from the logic comparator means.

Claim 32

A digital word checking apparatus for receiving and analyzing digital bit patterns and adpated for operation in responsive to commands from a digital computer, comprising: plural multibit local memories each operable independently of the computer for receiving from the computer and storing separate digital bit patterns representing data expected to be received, each such memory being separately addressable for the receipt of information from the computer; a clock source producing a signal having a frequency related to the operation rate of the local memories; means responsive to the computer command signal for applying the clock source signal to said local memories to produCe the bits of each digital pattern at the memory outputs in time sequential relation whereby the simultaneous occurrence of data information bits at the memory outputs may represent plural bits of a parallel-bit word; and logic comparator means jointly responsive to the bit patterns at the outputs of the local memories and the received data for generating error bit indications upon any discrepancy between the expected and received bit patterns.

Claim 33

A digital word checking apparatus for receiving and analyzing digital bit patterns and adpated for operation in responsive to commands from a digital computer, comprising: plural multibit local memories each operable independently of the computer for receiving from the computer and storing separate digital bit patterns representing data expected to be received, each such memory being separately addressable for the receipt of information from the computer; a clock source producing a signal having a frequency related to the operation rate of the local memories; means responsive to the computer command signal for applying the clock source signal to said local memories to produCe the bits of each digital pattern at the memory outputs in time sequential relation whereby the simultaneous occurrence of data information bits at the memory outputs may represent plural bits of a parallel-bit word; and logic comparator means jointly responsive to the bit patterns at the outputs of the local memories and the received data for generating error bit indications upon any discrepancy between the expected and received bit patterns.

Claim 34

The digital word checking apparatus of claim 22, further comprising: a second logic comparator means for generating error indications upon any discrepancy between the expected and received bit patterns.

Claim 35

The digital word checking apparatus of claim 23, further comprising: an error storage register for receiving the error indications from each respective logic comparator means at a rate corresponding to the clock source rate.

Claim 36

The digital word checking apparatus of claim 24, further comprising: means for producing a strobe signal for operating the error register at the clock pulse rate and in time displaced relation thereto for storing in the error register only such error indications as may be present at such displaced time.

Claim 37

A digital word checking apparatus for receiving and analyzing digital bit patterns and adpated for operation in response to commands from a digital computer, comprising: a multibit local memory operable independently of the computer for receiving from the computer and storing a digital bit pattern representing data expected to be received; a clock source producing a signal having a frequency related to the operation rate of the local memories; means responsive to a computer command signal for applying the clock source signal to the local memory to produce the bits of the digital pattern at the memory output in time sequential relation; logic comparator means jointly responsive to the bit pattern at the output of the local memory and the received signal for generating error bit indications upon any discrepancy between the expected and received bit patterns; means responsive to a computer command for generating a level control signal; and level comparator means jointly responsive to the level control signal and to one of the expected and received signals for producing an output signal upon occurrence of those portions of a received signal which corresponds to an expected signal level.

Claim 38

A digital word checking apparatus for receiving and analyzing digital bit patterns and adpated for operation in response to commands from a digital computer, comprising: a multibit local memory operable independently of the computer for receiving from the computer and storing a digital bit pattern representing data expected to be received; a clock source producing a signal having a frequency related to the operation rate of the local memories; means responsive to a computer command signal for applying the clock source signal to the local memory to produce the bits of the digital pattern at the memory output in time sequential relation; logic comparator means jointly responsive to the bit pattern at the output of the local memory and the received signal for generating error bit indications upon any discrepancy between the expected and received bit patterns; means responsive to a computer command for generating a level control signal; and level comparator means jointly responsive to the level control signal and to one of the expected and received signals for producing an output signal upon occurrence of those portions of a received signal which corresponds to an expected signal level.

Claim 39

The digital word checking appartus of claim 26, wherein: the level control signal generating means provides separate control signals representing maximum and minimum acceptable levels for the incoming signal; and the level comparator means is operable to generate an output signal representing acceptable signal levels only when the received incoming signal is below and above those maximum and minimum levels, respectively, upon occurrence of a strobe pulse.

Claim 40

A digital word checking apparatus for receiving and analyzing digital bit patterns and adapted for operation in response to commands from a digital computer, comprising: a local multibit memory including a multistage register operable independently of the computer for receiving from the computer and storing a digital bit pattern representing data expected to be received, the register being operable to advance the digital bit pattern therethrough in response to a clock signal; a clock source producing said clock signal; means responsive to a computer command signal for applying the clock source signal to the local memory so as to produce the bits of the digital pattern at the memory output in time sequential relation; logic comparator means jointly responsive to the bit pattern at the output of the local memory and the received signal for generating error bit indications upon any discrepancy between the expected and received bit patterns; an index register having a bit storage capacity corresponding to the bit storage capacity of the local multibit register; means responsive to a computer command for storing at least one marker bit in the index register; and means responsive to the digital bit pattern received from the computer for locating the marker bit within the index register at a position representing the length of the stored digital bit pattern.

Claim 41

A digital word checking apparatus for receiving and analyzing digital bit patterns and adapted for operation in response to commands from a digital computer, comprising: a local multibit memory including a multistage register operable independently of the computer for receiving from the computer and storing a digital bit pattern representing data expected to be received, the register being operable to advance the digital bit pattern therethrough in response to a clock signal; a clock source producing said clock signal; means responsive to a computer command signal for applying the clock source signal to the local memory so as to produce the bits of the digital pattern at the memory output in time sequential relation; logic comparator means jointly responsive to the bit pattern at the output of the local memory and the received signal for generating error bit indications upon any discrepancy between the expected and received bit patterns; an index register having a bit storage capacity corresponding to the bit storage capacity of the local multibit register; means responsive to a computer command for storing at least one marker bit in the index register; and means responsive to the digital bit pattern received from the computer for locating the marker bit within the index register at a position representing the length of the stored digital bit pattern.

Claim 42

The digital word checking apparatus of claim 28, further comprising: means responsive to a computer command for advancing the stored digital bit pattern through the local multibit register and for simultaneously advancing the market bit through the index register; and means responsive to the position of the marker bit for terminating advancement of the digital bit pattern upon arrival of the bits of such pattern at a desired position within the local multibit register.

Claim 43

The digital word checking apparatus of claim 28, wherein: the advancing means includes a load clock pulse generator responsive to a computer command for applying data advancing pulses to the index and local multibit registers.

Claim 44

A digital word generator and receiver apparatus for producing and receiving digital bit patterns at test points in response to commands from a digital control means, comprising: a plurality of independently operable local multibit memories having outputs each selectively connectable to separate test points for storing multibit digital patterns; a clock pulse source connected to said memories so as to clock the bits of said digital pattern in sequence to the memory outputs; logic compositor means associated with each of said local memories for receiving a digital bit pattern from a test point; switch means operable in response to a command from the control means for controllably coupling selected ones of the test points to either the local memory or the logic comparator means associated therewith; and means coupling the output of the local memory to the comparator means so as to produce error information at the output of said comparator means representing a discrepancy between the digital pattern received from a connected test point and the local memory.

Claim 45

A digital word generator and receiver apparatus for producing and receiving digital bit patterns at test points in response to commands from a digital control means, comprising: a plurality of independently operable local multibit memories having outputs each selectively connectable to separate test points for storing multibit digital patterns; a clock pulse source connected to said memories so as to clock the bits of said digital pattern in sequence to the memory outputs; logic compositor means associated with each of said local memories for receiving a digital bit pattern from a test point; switch means operable in response to a command from the control means for controllably coupling selected ones of the test points to either the local memory or the logic comparator means associated therewith; and means coupling the output of the local memory to the comparator means so as to produce error information at the output of said comparator means representing a discrepancy between the digital pattern received from a connected test point and the local memory.

Claim 46

The apparatus of claim 31, further comprising: an error memory coupled to the output of the logic comparator so as to store error bit information therefrom.

Claim 47

The apparatus of claim 32, further comprising: delay clock pulse means for delaying the application of clock pulses to said local memory when the logic comparator means is coupled to a test point.

Claim 48

The apparatus of claim 33, further comprising: means for varying the amount of delay of said delayed clock pulses from said clock pulses.