Automatic switching of storage protect keys

Claim 2

Apparatus for a central processing unit which executes programs in conjunction with an addressable main storage comprising a plurality of first registers each assigned to a predetermined block of locations in said main storage, means for loading said first registers with bytes of information, a second register, means responsive to the initial instruction fetch for a program execution by said central processing unit for transferring the contents of the one of the said first registers assigned the block of storage containing said instruction to said second register, and means responsive to subsequent instructions addressing said main storage for comparing said second register with the contents of the one of the said first registers assigned to the block of storage locations addressed by said subsequent instructions, whereby failure of said comparing means to produce an indication of a favorable compare reflects an attempt by the instruction then being executed to perform an operation prohibited relative to the said block of storage locations addressed by the said subsequent instruction.

Claim 3

Apparatus in accordance with claim 1 which further includes logic means responsive to a special byte in any of said first registers for producing an output indicative that a said subsequent instruction operation is to be permitted regardless of said comparing means output.

Claim 4

Apparatus in accordance with claim 1 which further includes means for transferring a byte from said central processing unit to said second register, and logic means responsive to a special byte in said second register for producing an output indicative that a said subsequent instruction operation is to be permitted regardless of said comparing means output.

Claim 5

Apparatus in accordance with claim 1 wherein said central processing unit is capable of handling multiple programs each having a priority level assigned thereto with control means permitting the said program having the highest said priority at any given time to operate said central processing unit, said apparatus further including a plurality of said second registers each corresponding to a respective priority level, and means responsive to said central processing unit control means for causing said comparing means to operate with the said second register corresponding to the priority level of the program being permitted to operate by said control means while retaining all other said second registers in their previous state.

Claim 6

Apparatus for a central processing unit having an addressable main storage and means for producing bytes of information composed of high order bits and low order bits comprising a plurality of first registers each assigned to a predetermined block of locations in said main storage, means responsive to said high order bits for selecting one of said first registers, means responsive to execution of an initializing instruction by said central processing unit for gating said low order bits into the selected one of the said first registers selected by said high order bits, a second register, means responsive to the first instruction of a program about to be executed by said central processing unit for transferring the contents of the said first register selected by said high order bits responsive means to said second register, means responsive to subsequent instructions for the said program for compaRing the one of the said first registers selected by said high order bits responsive means with said second register, and logic means responsive to said comparing means output for indicating that the operation intended by one of the said subsequent instructions is prohibited.

Claim 7

Apparatus for a central processing unit having an addressable main storage and means for producing bytes of information composed of high order bits and low order bits comprising a plurality of first registers each assigned to a predetermined block of locations in said main storage, means responsive to said high order bits for selecting one of said first registers, means responsive to execution of an initializing instruction by said central processing unit for gating said low order bits into the selected one of the said first registers selected by said high order bits, a second register, means responsive to the first instruction of a program about to be executed by said central processing unit for transferring the contents of the said first register selected by said high order bits responsive means to said second register, means responsive to subsequent instructions for the said program for compaRing the one of the said first registers selected by said high order bits responsive means with said second register, and logic means responsive to said comparing means output for indicating that the operation intended by one of the said subsequent instructions is prohibited.

Claim 8

Apparatus in accordance with claim 5 wherein said logic means includes means responsive to a special byte in the said first register selected by said high order bit responsive means for preventing production of said prohibited operation indicating signal.

Claim 9

Apparatus in accordance with claim 5 which further includes means responsive to a controlling instruction from said central processing unit for transferring a special byte to said second register, and said logic means being responsive to said special byte in said second register for preventing production of said prohibited operation indicating signal.

Claim 10

Apparatus in accordance with claim 5 wherein said central processing unit executes programs having priority levels assigned thereto with control means interrupting execution of a program having a given priority level in favor of executing a program having a higher priority level, said apparatus further including a plurality of said second registers each assigned a respective said priority level, and means responsive to said control means for allowing said comparing means to compare (a) the one of the said first register selected by said high order bits in the instruction currently being executed with (b) the said second registers assigned the same priority level as the program currently being executed.