Patent US3824378A successfully refreshed from Google Patents.
US3824378A
Expired / Lapsed
US
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Electronic counter
Assignee: Presin Co Inc
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Filing: 1972-09-13
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Granted: 1974-07-16
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Expires: 1992-09-13
Abstract
Abstract A battery-sustained multiple level electronic counter is provided which includes an N-bit memory and an address counter and control for the memory. A single bank of a plurality of binary code decimal input switches are provided which are set for preset levels to be stored in the memory utilizing a much smaller number of address-select binary code decimal switches coupled to the address counter. The number of digits of the address-select switches corresponds to the number of preset levels desired to be measured. An N-digit binary code decimal counter and multiplexer is fed by the count input and coupled to a comparator which is also coupled to the memory. Signals are fed to the comparator from the binary code counter and multiplexer and the N-bit memory under the control of the address counter and control to provide an output when a preset level is hit. A hit counter is also provided which is coupled to the output of the comparator for resetting the binary code counter and multiplexer. The system can be modified using remote actuation so that the preset values cannot be tampered with, once they are set, or a single preset level can be utilized, or the system can operate as a totalizer.
Inventors
- 👤 G Johnson
- 👤 M Teichner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 19:40
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/64; H03K23/66; G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/045
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
247 words
A multilevel preset electronic counter for providing an output at each preset level, comprising a. a memory, b. a single bank of binary coded decimal input switches coupled to said memory, the number of which corresponds to the largest value preset number desired, for providing an output code for the decimal digit set in each switch and the number set in a plurality of said input switches, c. address counter and control means coupled to said memory for controllably storing a plurality of preset levels set by said input switches in said memory and controlling the output of said memory, d. address select switching means comprising a second binary code decimal switch means in which the number of switches corresponds to one for each decimal of preset levels which are to be stored in said memory, said address select switching means coupled to said address counter and control means for controlling the entry of preset numbers from said bank of binary coded decimal input switches, e. comparator means coupled to said memory, f. a binary coded counter and multiplexer coupled to said comparator means and said address counter and control means and having a count input applied thereto for generating a multiplex start signal which initiates a counter to memory comparison on the input of each count applied thereto, and g. output gating means coupled to said comparator means for producing an output signal when a preset number stored in said memory is reached by said counter.
Claim 2
Dependent Claim
247 words
A multilevel preset electronic counter for providing an output at each preset level, comprising a. a memory, b. a single bank of binary coded decimal input switches coupled to said memory, the number of which corresponds to the largest value preset number desired, for providing an output code for the decimal digit set in each switch and the number set in a plurality of said input switches, c. address counter and control means coupled to said memory for controllably storing a plurality of preset levels set by said input switches in said memory and controlling the output of said memory, d. address select switching means comprising a second binary code decimal switch means in which the number of switches corresponds to one for each decimal of preset levels which are to be stored in said memory, said address select switching means coupled to said address counter and control means for controlling the entry of preset numbers from said bank of binary coded decimal input switches, e. comparator means coupled to said memory, f. a binary coded counter and multiplexer coupled to said comparator means and said address counter and control means and having a count input applied thereto for generating a multiplex start signal which initiates a counter to memory comparison on the input of each count applied thereto, and g. output gating means coupled to said comparator means for producing an output signal when a preset number stored in said memory is reached by said counter.
Claim 3
Dependent Claim
45 words
The counter set forth in claim 1 having an enter button coupled to said address counter and control means which is depressed each time a preset number is stored in said memory from said binary code decimal input switches and said address select switching means.
Claim 4
Dependent Claim
42 words
The counter set forth in claim 1 having a word end output corresponding to the end of each preset number from said address counter and control means coupled to said comparator for providing an output from said comparator for every preset level.
Claim 5
Dependent Claim
44 words
The counter set forth in claim 3 having a word output from said address counter and control means coupled to said output gating means for passing an output from said comparator means through said output gating means on the coincidence of each preset number.
Claim 6
Dependent Claim
44 words
The counter set forth in claim 4 having a hit counter coupled to the output of said comparator and the input binary coded counter and multiplexer for resetting said binary coded counter and multiplexer after all of the plurality of preset levels are reached.
Claim 7
Dependent Claim
15 words
The counter set forth in claim 5 which is powered from a single battery source.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-07-15 | 1978-01-14 | 1978-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-07-15 | 1982-01-14 | 1982-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-07-15 | 1986-01-14 | 1986-07-16 | $7700.00 | Window Closed / Lapsed |