Charge transfer device analog matched filter

Claim 2

An analog matched filter comprising: a semiconductor substrate; an insulating layer on said substrate; a multiphase clock charge transfer device analog shift register on said substrate defining a plurality of delay stages; means for applying input signals to said shift register for storage as electrical charge in successive ones of said delay stages; each said delay stage having a plurality of electrodes separated from said substrate by said insulating layer, at least one said electrode of each stage defined by first and a second spaced portions so dimensioned relative to each other to define a selected weighting factor such that the weighting factors of all said stages in combination define a preselected filter impulse response matched to a predetermined input signal; clock pulse generator means for generating multiphase clock pulses; means connecting said clock pulse generator means to said electrodes for application of clock pulses thereto for shifting said input signals between said delay stages, said clock pulses supplying charging current to said electrodes of each stage dependent on the magnitude of signal charge stored at that stage; said connecting means including a first clock line connected to all said first electrode portions and a second clock line connected to all said second electrode portions; and detector means comprising a differential amplifier connected across said first and second clock lines for detecting differential voltage thereacross produced responsive to application of clock pulses to said electrode portions.

Claim 3

An analog matched filter as set forth in claim 1 including nulling means connected to said differential amplifier wherein said differential amplifier measures only differential voltage produced across said first and second clock lines in response to the signal charge in each of said delay stages.

Claim 4

An analog matched filter as set forth in claim 2 wherein said nulling means comprises a capacitor connected between one of said first and second clock lines and a circuit ground.

Claim 5

In a charge transfer device analog matched filter integrated on a semiconductor substrate having an insulating layer on one surface thereof, a plurality of delay stages disposed adjacent to said one surface, each said delay stage including spaced apart electrodes on said insulating layer; means for applying input signals to an input of said filter for storage in delay stages thereof as electric charge dependent on input signal amplitude; and clock pulse generating means for applying clock pulses of different phases to said electrodes of each stage to shift said stored charges between said delay stages from said input to an output of said filter said clock pulses supplying charging current to said electrodes related to charge stored at that stage; bridge detector means comprising: a. contact means on said substrate for receiving one phase of said multiphase clock pulses; b. first and second clock lines each connected to said contact means through a respective preselected electrical impedance; c. said electrodes in each of said delay stages including weighting means defined by an elongated electrode having two spaced apart portions defining its elongate dimension, the dimension ratio between said electrode portions defining a weighting function of unity or less, one of said electrode portions defining positive weighting and the other portion defining negative weighting; means connecting said one portions of all said weighting electrodes in common to said first clock line; means connecting the said other portions of all said weighting electrodes in common to said second clock line; said first clock line effective to sum all of the positively weighted signal-related charging currents and said second clock line effective to sum all of said negatively weighted signal-related charging currents; and d. means connecting a differential amplifier across said first and second clock lines for generating an output signal responsive to differential in voltages developed across said impedances by said summed currents.

Claim 6

In a charge transfer device analog matched filter integrated on a semiconductor substrate having an insulating layer on one surface thereof, a plurality of delay stages disposed adjacent to said one surface, each said delay stage including spaced apart electrodes on said insulating layer; means for applying input signals to an input of said filter for storage in delay stages thereof as electric charge dependent on input signal amplitude; and clock pulse generating means for applying clock pulses of different phases to said electrodes of each stage to shift said stored charges between said delay stages from said input to an output of said filter said clock pulses supplying charging current to said electrodes related to charge stored at that stage; bridge detector means comprising: a. contact means on said substrate for receiving one phase of said multiphase clock pulses; b. first and second clock lines each connected to said contact means through a respective preselected electrical impedance; c. said electrodes in each of said delay stages including weighting means defined by an elongated electrode having two spaced apart portions defining its elongate dimension, the dimension ratio between said electrode portions defining a weighting function of unity or less, one of said electrode portions defining positive weighting and the other portion defining negative weighting; means connecting said one portions of all said weighting electrodes in common to said first clock line; means connecting the said other portions of all said weighting electrodes in common to said second clock line; said first clock line effective to sum all of the positively weighted signal-related charging currents and said second clock line effective to sum all of said negatively weighted signal-related charging currents; and d. means connecting a differential amplifier across said first and second clock lines for generating an output signal responsive to differential in voltages developed across said impedances by said summed currents.

Claim 7

A semiconductor charge transfer device analog matched filter having a plurality of delay stages defined at one surface of a semiconductor substrate covered by insulating layer, each delay stage including spaced apart electrodes on said insulating layer; means for applying input signals to said filter for storage as electrical charge in successive ones of said delay stages; multiphase clock pulse generaTing means connected to said electrodes for effecting transfer of said stored charge between said delay stages; in each said delay stage one of said electrodes including first and second spaced apart portions having respective areas, the ratio of the area of said first electrode portion to that of said second electrode portion in each stage defining a selected weighting factor for that stage not greater than unity; a first clock line connecting all said first electrode portions and a second clock line connecting all said second electrode portions; respective first and second impedance means connecting said first and second clock lines to one phase of said multiphase clock pulse generator means for applying charging current to said first and second electrode portions, said charging currents supplied to said first and second electrode portions of each stage having a magnitude equal to the sum of a reference current and a current dependent on the signal charge stored at that stage, said charging currents causing respective voltage drops across said first and second impedances dependent on the sums of said currents supplied to the first electrode portions and to the second electrode portions respectively; and means connected to said first and second clock lines for detective differential in said voltage drop across said first and second impedances to provide a correlated output signal responsive to a said input signal which is matched with said filter impulse response.

Claim 8

A semiconductor charge transfer device analog matched filter having a plurality of delay stages defined at one surface of a semiconductor substrate covered by insulating layer, each delay stage including spaced apart electrodes on said insulating layer; means for applying input signals to said filter for storage as electrical charge in successive ones of said delay stages; multiphase clock pulse generaTing means connected to said electrodes for effecting transfer of said stored charge between said delay stages; in each said delay stage one of said electrodes including first and second spaced apart portions having respective areas, the ratio of the area of said first electrode portion to that of said second electrode portion in each stage defining a selected weighting factor for that stage not greater than unity; a first clock line connecting all said first electrode portions and a second clock line connecting all said second electrode portions; respective first and second impedance means connecting said first and second clock lines to one phase of said multiphase clock pulse generator means for applying charging current to said first and second electrode portions, said charging currents supplied to said first and second electrode portions of each stage having a magnitude equal to the sum of a reference current and a current dependent on the signal charge stored at that stage, said charging currents causing respective voltage drops across said first and second impedances dependent on the sums of said currents supplied to the first electrode portions and to the second electrode portions respectively; and means connected to said first and second clock lines for detective differential in said voltage drop across said first and second impedances to provide a correlated output signal responsive to a said input signal which is matched with said filter impulse response.

Claim 9

A semiconductor charge transfer device according to claim 5, including nulling means connected to said differential detective means for eliminating the effects of said reference currents from said differential voltage measurement.

Claim 10

A semiconductor charge transfer device according to claim 5, wherein said detection means comprises an integrated circuit high gain differential amplifier, and means connecting said first and second clock lines to respective non-inverting and inverting inputs of said amplifier.

Claim 11

A semiconductor charge transfer device according to claim 7, further including a nulling capacitor connected to one of said first and second clock lines for eliminating effects of said reference currents on the output of said amplifier.