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Patent US3816657A successfully refreshed from Google Patents.
US3816657A
Expired / Lapsed
US
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Differential phase-shift-keyed communication system
Assignee: National Aeronautics and Space Administration
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Filing: 1972-10-12
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Granted: 1974-06-11
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Expires: 1992-10-12
Abstract
Abstract A communication system using differential phase-shift-keying (DPSK) transmits and receives binary data without requiring timing or phase reference signals. The system encodes and modulates the data at the transmitter, and decodes and demodulates the data at the receiver, without ambiguity as to the data content.
Inventors
- 👤 J Fletcher
- 👤 P Hopkins
- 👤 W Wallingford
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 18:25
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/18; H04L27/20; H04L27/2032; H04L27/2053; H04L27/2057
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
276 words
A quadriphase differential phase-shift-keyed communication system, said system including: a. transmitter means for transmission of a phase-shift-keyed signal formed from input data bits wherein the input data bits are furnished to said transmitter means over two channels as two streams of incoming data bits for each successive transmission interval, said transmitter means comprising 1. carrier source means for providing a carrier signal of a predetermined frequency; 2. encoding means responsive to the input data bits for forming a two bit phase increment signal having one of four values in accordance with the input data bits; 3. means for modulating the phase increment signal onto the carrier signal to form the transmitted signal representing the data bits by the phase increment signal; said encoding means comprising first comparator means for forming the first bit of the phase increment signal by comparing a first incoming data bit with the first bit of the phase increment signal formed during the preceding transmission interval, and second comparator means for forming the second bit of the phase increment signal by comparing a second incoming data bit with the second bit of the phase increment signal formed during the preceding transmission interval; and b. receiver means for receiving the signal from said transmitter means, said receiver means comprising 1. means for deriving a local reference signal from the received signal; 2. demodulator means for demodulating the received signal with the local reference signal to form a received phase increment signal having one of four states; and 3. decoding means responsive to the received phase increment signal for forming output data bits in accordance with the state of the received phase increment signal.
Claim 2
Dependent Claim
276 words
A quadriphase differential phase-shift-keyed communication system, said system including: a. transmitter means for transmission of a phase-shift-keyed signal formed from input data bits wherein the input data bits are furnished to said transmitter means over two channels as two streams of incoming data bits for each successive transmission interval, said transmitter means comprising 1. carrier source means for providing a carrier signal of a predetermined frequency; 2. encoding means responsive to the input data bits for forming a two bit phase increment signal having one of four values in accordance with the input data bits; 3. means for modulating the phase increment signal onto the carrier signal to form the transmitted signal representing the data bits by the phase increment signal; said encoding means comprising first comparator means for forming the first bit of the phase increment signal by comparing a first incoming data bit with the first bit of the phase increment signal formed during the preceding transmission interval, and second comparator means for forming the second bit of the phase increment signal by comparing a second incoming data bit with the second bit of the phase increment signal formed during the preceding transmission interval; and b. receiver means for receiving the signal from said transmitter means, said receiver means comprising 1. means for deriving a local reference signal from the received signal; 2. demodulator means for demodulating the received signal with the local reference signal to form a received phase increment signal having one of four states; and 3. decoding means responsive to the received phase increment signal for forming output data bits in accordance with the state of the received phase increment signal.
Claim 3
Dependent Claim
28 words
encoding means responsive to the input data bits for forming a two bit phase increment signal having one of four values in accordance with the input data bits;
Claim 4
Dependent Claim
28 words
encoding means responsive to the input data bits for forming a two bit phase increment signal having one of four values in accordance with the input data bits;
Claim 5
Dependent Claim
25 words
demodulator means for demodulating the received signal with the local reference signal to form a received phase increment signal having one of four states; and
Claim 6
Dependent Claim
25 words
demodulator means for demodulating the received signal with the local reference signal to form a received phase increment signal having one of four states; and
Claim 7
Dependent Claim
57 words
The structure of claim 1, wherein said first comparator means comprises: a. means for storing the first bit of the phase increment signal formed during the preceding transmission first adder interval; and b. first adder means for forming the first bit of the phase increment signal when the stored first bit and the incoming data bit differ.
Claim 8
Dependent Claim
32 words
The structure of claim 2, wherein said first adder means comprises: means for forming a carry output signal when the stored first bit and the incoming data bit are logic ''''1'''' levels.
Claim 9
Dependent Claim
25 words
decoding means responsive to the received phase increment signal for forming output data bits in accordance with the state of the received phase increment signal.
Claim 10
Dependent Claim
25 words
decoding means responsive to the received phase increment signal for forming output data bits in accordance with the state of the received phase increment signal.
Claim 11
Dependent Claim
116 words
means for modulating the phase increment signal onto the carrier signal to form the transmitted signal representing the data bits by the phase increment signal; said encoding means comprising first comparator means for forming the first bit of the phase increment signal by comparing a first incoming data bit with the first bit of the phase increment signal formed during the preceding transmission interval, and second comparator means for forming the second bit of the phase increment signal by comparing a second incoming data bit with the second bit of the phase increment signal formed during the preceding transmission interval; and b. receiver means for receiving the signal from said transmitter means, said receiver means comprising
Claim 12
Dependent Claim
116 words
means for modulating the phase increment signal onto the carrier signal to form the transmitted signal representing the data bits by the phase increment signal; said encoding means comprising first comparator means for forming the first bit of the phase increment signal by comparing a first incoming data bit with the first bit of the phase increment signal formed during the preceding transmission interval, and second comparator means for forming the second bit of the phase increment signal by comparing a second incoming data bit with the second bit of the phase increment signal formed during the preceding transmission interval; and b. receiver means for receiving the signal from said transmitter means, said receiver means comprising
Claim 13
Dependent Claim
60 words
The structure of claim 3, wherein said second comparator means comprises: a. means for storing the second bit of the phase increment signal formed during the preceding transmission interval; b. second adder means for digitally adding the stored second bit, the second incoming data bit and the carry output signal to form the second bit of the phase increment signal.
Claim 14
Dependent Claim
109 words
The system of claim 1 wherein said decoding means comprises mEans for forming a two bit output data signal, said decoding means further comprising: a. first receiver comparator means for forming the first bit of the output data signal by comparing the first bit of the currently received phase increment signals with the first bit of the received phase increment signal from the preceding transmission interval; and b. second receiver comparator means for forming the second bit of the output data signal by comparing the second bit of the currently received phase increment signal with the second bit of the received phase increment signal from the preceding transmission interval.
Claim 15
Dependent Claim
68 words
The structure of claim 5, wherein said first receiver comparator means comprises: a. means for storing the first bit of the received phase increment signal from the preceding transmission interval; and b. first subtractor means for forming the first bit of the output data signal when the stored first bit of the received phase increment signal and the first bit of the currently received phase increment signal differ.
Claim 16
Dependent Claim
131 words
The structure of claim 6, wherein said second receiver comparator means comprises a. storage means for storing the second bit of the received phase increment signal from the preceding transmission interval; and b. second subtractor means for digitally subtracting said stored second bit in said storage means from the currently received second bit of the phase increment signal, said second subtractor means including a three-input adder means for receiving the stored second bit in said storage means at one input, the currently received second bit of the phase increment signal at a second input, and a constant logic ''''1'''' signal at a third input thereof, and said adder means forming a carry output subtract signal when at least two of the signals to the said adder inputs are logic ''''1'''' signals.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-06-10 | 1977-12-10 | 1978-06-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-06-10 | 1981-12-10 | 1982-06-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-06-10 | 1985-12-10 | 1986-06-11 | $7700.00 | Window Closed / Lapsed |