US3813651A
Expired / Lapsed
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Data processing system
Assignee: Toshiba Corp
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Filing: 1972-12-26
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Granted: 1974-05-28
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Expires: 1992-12-26
Abstract
Abstract A data processing system comprising an assembly of buses for interconnecting a plurality of units, the units including data processing units, a memory unit and peripheral data processing units, the data processing units being connected in series with each other via a signal line and being further connected to said bus assembly in parallel relationship with each other. A bus control unit is provided for delivering a ''''who'''' signal (which is used for detecting a requesting unit) to the first one of said serially connected data processing units when said unit requests the use of said bus assembly. Further provided is an interface circuit unit which receives the ''''who'''' signal from the signal line and which, when any of the units does not make its own request for the use of the bus assembly upon receipt of the ''''who'''' signal, transmits said ''''who'''' signal to the immediately following unit and, when the first mentioned unit requests the use of the bus assembly for itself, prevents said ''''who'''' signal from being further transmitted, and selects another unit associated with the address signal delivered from said bus requesting unit and interconnects both units through said bus assembly.
Inventors
- 👤 H Yamada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 02:31
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F13/36; G06F13/368; G06F13/37; G06F13/38
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
395 words
A data processing system comprising: a plurality of data processing units including an arithmetic operation unit, a memory unit and peripheral data processing units, said data processing units being connected in series with each other by means of a signal line; a main bus assembly including a request bus, a master synchronization bus, a slave synchronization bus, and a data bus for connecting said data processing units in parallel so as to effect exchange of data therebetween; a main bus control unit for delivering a ''''who'''' signal to the first unit of said serially connected data processing units upon receipt of a request signal via said request bus, said ''''who'''' signal being used for detecting a unit which has requested the use of buses, said main bus control unit having a first NAND gate including a first input terminal connected to said request bus and a second input terminal connected to said master synchronization bus, a second NAND gate including an input terminal connected to said slave synchronization bus, a third NAND gate icluding a first input terminal connected to said master synchronization bus and a second input terminal connected to the output terminal of said second NAND gate, and a fourth NAND gate including a first input terminal connected to the output terminal of said first NAND gate, a second input terminal connected to the output terminal of said third NAND gate and a ''''who'''' signal output terminal connected to the input terminal of said first unit; and a plurality of first interface circuits each of which is associated with said respective data processing units, said interface circuits being connected to receive said ''''who'''' signal via said signal line which transmits the ''''who'''' signal to the immediately following data processing unit when a data processing unit receiving the ''''who'''' signal does not generate a request signal to said request bus for the use of said main bus assembly, and includes means to prevent the ''''who'''' signal from being further transferred to the immediately following data processing unit when a data processing unit receiving ''''who'''' signal has already generated a request signal to said request bus, and means to select a called data processing unit associated with the address signal given forth by the request signal generated data processing unit so as to connect the desired two data processing units through the main bus assembly.
Claim 2
Dependent Claim
395 words
A data processing system comprising: a plurality of data processing units including an arithmetic operation unit, a memory unit and peripheral data processing units, said data processing units being connected in series with each other by means of a signal line; a main bus assembly including a request bus, a master synchronization bus, a slave synchronization bus, and a data bus for connecting said data processing units in parallel so as to effect exchange of data therebetween; a main bus control unit for delivering a ''''who'''' signal to the first unit of said serially connected data processing units upon receipt of a request signal via said request bus, said ''''who'''' signal being used for detecting a unit which has requested the use of buses, said main bus control unit having a first NAND gate including a first input terminal connected to said request bus and a second input terminal connected to said master synchronization bus, a second NAND gate including an input terminal connected to said slave synchronization bus, a third NAND gate icluding a first input terminal connected to said master synchronization bus and a second input terminal connected to the output terminal of said second NAND gate, and a fourth NAND gate including a first input terminal connected to the output terminal of said first NAND gate, a second input terminal connected to the output terminal of said third NAND gate and a ''''who'''' signal output terminal connected to the input terminal of said first unit; and a plurality of first interface circuits each of which is associated with said respective data processing units, said interface circuits being connected to receive said ''''who'''' signal via said signal line which transmits the ''''who'''' signal to the immediately following data processing unit when a data processing unit receiving the ''''who'''' signal does not generate a request signal to said request bus for the use of said main bus assembly, and includes means to prevent the ''''who'''' signal from being further transferred to the immediately following data processing unit when a data processing unit receiving ''''who'''' signal has already generated a request signal to said request bus, and means to select a called data processing unit associated with the address signal given forth by the request signal generated data processing unit so as to connect the desired two data processing units through the main bus assembly.
Claim 3
Dependent Claim
155 words
The data processing system according to claim 1 wherein the bus assembly includes a request bus for interconnecting the bus control unit and all of the units with a bus requesting signal delivered from any of the units; a ''''who'''' signal synchronization bus through which, a ''''who'''' signal synchronization signal is sent to the bus control unit from a bus-requesting unit after the receipt of said ''''who'''' signal; a data bus through which exchange of data takes place between the units; an address bus for conducting the address signal delivered from the bus-requesting unit to the selected responding unit associated with said address; a master synchronization bus for transmitting a master synchronization signal to the selected responding unit and bus control unit; and a slave synchronization unit for conducting a slave synchronization signal indicating completion of the receipt and delivery of data by the selected responding unit to the bus-requesting unit and bus control unit.
Claim 4
Dependent Claim
61 words
The data processing system according to claim 1 wherein the bus control unit is provided with a first gating circuit for giving forth a ''''who'''' signal upon receipt of a bus-requesting signal from any of the units and for stopping the generation of said ''''who'''' signal after completion of exchange of data between the bus-requesting unit and a selected reSponding unit.
Claim 5
Dependent Claim
144 words
The data processing system according to claim 1 wherein: said first interface circuit is provided in those of the units which output a bus requesting signal and includes means for transmitting the ''''who'''' signal to the immediately following unit when any of the units does not output the requesting signal for the use of the bus assembly, means for preventing said ''''who'''' signal from being supplied to said immediately following unit when the first mentioned unit requests the use of the bus assembly for itself, and means for supplying the data delivered from the bus-requesting unit to the data bus; and a second interface circuit is disposed in those of the units responsive to the data delivered from the bus-requesting unit so as to make a response to said data and to connect the bus-requesting unit and selected responding unit through the bus assembly.
Claim 6
Dependent Claim
207 words
The data processing system according to claim 4 wherein a first interface circuit is associated with each of the units, and a first interface circuit includes a flip-flop circuit which is set upon receipt of a bus-requesting signal of its own unit to supply said bus-requesting signal to the request bus; a second gating circuit which, when the flip-flop circuit is reset upon receipt of the ''''who'''' signal, passes said ''''who'''' signal to the immediately following unit and, when the flip-flop circuit is set, prevents said ''''who'''' signal from being conducted to said immediately following unit; a third gating circuit which, when the flip-flop circuit receives said ''''who'''' signal in a set state, generates a master synchronization signal which is synchronized with an internal timing signal associated with the bus-requesting unit; a circuit for generating a ''''who'''' signal synchronization signal synchronized with the ''''who'''' signal in connection with the bus-requesting unit when supplied with said ''''who'''' signal; and a fourth gating circuit responsive to the completion of operation of the selected responding unit for resetting the flip-flop circuit upon receipt of a slave synchronization signal after completion of the operation of the selected responding unit, which operation is determined by the data delivered from the bus-requesting unit.
Claim 7
Dependent Claim
102 words
The data processing system according to claim 4 wherein the second interface circuit includes a comparing circuit for comparing its own address with the one delivered from the bus-requesting unit through the address bus; a fifth gating circuit for generating a signal to actuate said selected responding unit when the comparing circuit produces an output signal and the master synchronization bus is supplied with a master synchronization signal from the first interface circuit; and a sixth gating circuit for generating a slave synchronization signal after said comparing circuit generates an output indicating the completion of the operation of said selected responding unit.
Claim 8
Dependent Claim
41 words
The data processing system according to claim 1 wherein there is further provided an interruption unit which is connected to the bus assembly in parallel relationship with the other units temporarily to store an interruption-requesting signal delivered from the bus-requesting unit.
Claim 9
Dependent Claim
95 words
The data processing system according to claim 7 wherein the interruption unit includes a comparing circuit for comparing its own address and the one delivered from the bus-requesting unit, and which when both addresses synchronize with each other, generates a signal; a decoder for decoding a signal indicating the desired signal level representing the content of interruption delivered from the bus-requesting unit through the data bus; and a plurality of memory devices for storing said desired signal level representing the content of interruption upon the simultaneous arrival of outputs of said comparing circuit and decoder.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-05-27 | 1977-11-26 | 1978-05-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-05-27 | 1981-11-26 | 1982-05-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-05-27 | 1985-11-26 | 1986-05-28 | $7700.00 | Window Closed / Lapsed |