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US3710326A Expired / Lapsed US ⏱️ 0.0 years remaining

Preferential offering signal processing system

Assignee: Yokogawa Electric Corp
•
Filing: 1970-06-12
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Granted: 1973-01-09
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Expires: 1990-06-12
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Abstract

Abstract A system for feeding offering (input) signals from a plurality of groups of offering (input) terminals to a CPU. A control circuit is associated with each terminal and these control circuits are divided into groups corresponding to the terminal. The groups of control circuits are selectively fed select signals and the CPU sends out polling signals sequentially to the control circuits of each group. Each of the control circuits contains an AND circuit which is enabled to pass a signal to the CPU when its control circuit receives a polling and a select signal along with an offering signal at its associated terminal.

Inventors

  • 👤 K Nezu
  • 👤 Y Tochitani

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 07:42
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F13/26

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 151 words
In a system for feeding input signals to a receiving device from a plurality of groups of input terminals through gating circuits respectively associated with the groups of input terminals by enabling said gating circuits with select and polling signals and disabling said gating circuits with reset signals, the improvement where each said gating circuit comprises: a plurality of bistable circuits respectively associated with the input terminals associated with said gating circuit, each said bistable circuit being connected to its associated input terminal for storing an input signal at said terminal; a plurality of first gates, each of which is connected to the output of an associated bistable circuit and adapted to pass a signal stored therein upon receiving a polling and a select signal; and, a plurality of second gates, each of which is connected for resetting an associated bistable circuit in response to a polling and a reset signal.
Claim 2
Dependent Claim 151 words
In a system for feeding input signals to a receiving device from a plurality of groups of input terminals through gating circuits respectively associated with the groups of input terminals by enabling said gating circuits with select and polling signals and disabling said gating circuits with reset signals, the improvement where each said gating circuit comprises: a plurality of bistable circuits respectively associated with the input terminals associated with said gating circuit, each said bistable circuit being connected to its associated input terminal for storing an input signal at said terminal; a plurality of first gates, each of which is connected to the output of an associated bistable circuit and adapted to pass a signal stored therein upon receiving a polling and a select signal; and, a plurality of second gates, each of which is connected for resetting an associated bistable circuit in response to a polling and a reset signal.
Claim 3
Dependent Claim 61 words
The system as recited in claim 1 wherein each said gating circuit further comprises: an OR circuit connected to the outputs of each said bistable circuit in said gating circuit and whose output is connected to said receiving device for signalling said receiving device of the occurrence of an input signal at one of the terminals associated with said gating circuit.
Claim 4
Dependent Claim 39 words
The system as recited in claim 1 wherein each said gating circuit further comprises: an OR circuit connected for receiving the outputs of said first gates in said gating circuit and for passing said outputs to said receiving device.
Claim 5
Dependent Claim 31 words
The system as recited in claim 2 wherein the outputs of said OR circuits in said plurality of gating circuits are connected in common as an input to said receiving device.
Claim 6
Dependent Claim 31 words
The system as recited in claim 3 wherein the outputs of said OR circuits in said plurality of gating circuits are connected in common as an input to said receiving device.
Claim 7
Dependent Claim 37 words
The system as recited in claim 4 wherein said select signals are successively fed to said gating circuits as inputs to their first gates in response to a signal at said common input of said receiving device.
Claim 8
Dependent Claim 46 words
The system as recited in claim 4 where said polling signals are successively fed to the first and second gates associated with the plurality of bistable circuits in each of said gating circuits in response to a signal at said common input of said receiving device.
Claim 9
Dependent Claim 34 words
The system as recited in claim 5 wherein said second gates in each said gating circuit are fed a reset signal in response to a signal at said common input of said receiving device.

References Cited (Backward Citations)

US3396372A Cited
US3456244A Cited
US3512133A Cited
US3539998A Cited
US3509539A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-01-09 1976-07-10 1977-01-09 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-01-09 1980-07-10 1981-01-09 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-01-09 1984-07-10 1985-01-09 $7700.00 Window Closed / Lapsed

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