Controller program editor

Claim 2

In a program loader for a programmable controller having a read-write memory which stores at a set of memory locations instructions that comprise a controller program, the combination comprising: a first temporary storage connected to said read-write memory to receive and store an instruction read from an addressed memory location in said read-write memory; a second temporary storage connected to receive and store an instruction read from said read-write memory; a memory address counter connected to said read-write memory to selectively address memory locations therein; and a control circuit which includes first means connected to said read-write memory and said memory address counter to sequentially read out of memory each instruction in said set to said first and second temporary storages, and second means connected to said read-write memory and said first and second temporary storages to sequentially load each instruction stored in said first and second temporary storages back into said read-write memory at a different memory location.

Claim 3

The program loader as recited in claim 1 which includes: an input circuit operable to generate a manually selected I/O address; a comparator circuit having a first set of input terminals connected to said read-write memory to receive the I/O address in each of the instructions read therefrom, a second set of input terminals connected to said input circuit to receive the I/O address generated thereby, and an output terminal; and a flip-flop having a first input terminal connected to a logic input bus in the programmable controller to which the program loader is connected, and a second input terminal connected to said comparator circuit output terminal, wherein the comparator circuit is operable to change the logic state of its output terminal when the I/O addresses applied to its first and second input terminal sets are identical and said flip-flop is operable to store the logic condition of said logic input bus when the comparator output changes logic state.

Claim 4

incrementing a memory address counter to address another memory location;

Claim 5

incrementing a memory address counter to address another memory location;

Claim 6

transferring said instructions stored in said first temporary storage to a second temporary storage;

Claim 7

transferring said instructions stored in said first temporary storage to a second temporary storage;

Claim 8

The program loader as recited in claim 2 in which an indicator light is connected to said flip-flop to provide visual indication of the stored logic state.

Claim 9

In a program loader for a programmable controller having a read-write memory which stores at a set of memory locations instructions that comprise a controller program, the combination comprising: a first temporary storage connected to said read-write memory to receive and store an instruction read from an addressed memory location in said read-write memory; a second temporary storage connected to receive and store an instruction read from said read-write memory; a memory address counter connected to said read-write memory to selectively address memory locations therein; an input circuit operable to generate a manually selected instruction; a memory address display connected to said memory address counter; a comparator circuit having a first set of input terminals connected to said read-write memory, a second set of input terminals connected to said input circuit to receive an instruction from said input circuit, and an output terminal, said comparator circuit being operable to generate a first logic state at its output terminal when the instructions applied to its first and second input terminal sets are identical, and to generate a second logic state at its output terminal when the instructions applied to its first and second input terminal sets differ; a control circuit connected to said first and second temporary storages, said comparator circuit output terminal, and said memory address counter, said control circuit being operable in a first mode to shift the memory location of a set of said instructions by sequentially reading out of memory each instruction in said set, storing each in one Of said temporary storages, and loading each back into said read-write memory at a different memory location, and wherein said control circuit is operable in a second mode in which it is responsive to said second logic state generated at said comparator output terminal to repeatedly increment said memory address counter and to thereby read successive instructions of said controller program out of said read-write memory to said comparator circuit, and said control circuit is responsive to said first logic state generated at said comparator output terminal to stop incrementing said memory address counter.

Claim 10

In a program loader for a programmable controller having a read-write memory which stores at a set of memory locations instructions that comprise a controller program, the combination comprising: a first temporary storage connected to said read-write memory to receive and store an instruction read from an addressed memory location in said read-write memory; a second temporary storage connected to receive and store an instruction read from said read-write memory; a memory address counter connected to said read-write memory to selectively address memory locations therein; an input circuit operable to generate a manually selected instruction; a memory address display connected to said memory address counter; a comparator circuit having a first set of input terminals connected to said read-write memory, a second set of input terminals connected to said input circuit to receive an instruction from said input circuit, and an output terminal, said comparator circuit being operable to generate a first logic state at its output terminal when the instructions applied to its first and second input terminal sets are identical, and to generate a second logic state at its output terminal when the instructions applied to its first and second input terminal sets differ; a control circuit connected to said first and second temporary storages, said comparator circuit output terminal, and said memory address counter, said control circuit being operable in a first mode to shift the memory location of a set of said instructions by sequentially reading out of memory each instruction in said set, storing each in one Of said temporary storages, and loading each back into said read-write memory at a different memory location, and wherein said control circuit is operable in a second mode in which it is responsive to said second logic state generated at said comparator output terminal to repeatedly increment said memory address counter and to thereby read successive instructions of said controller program out of said read-write memory to said comparator circuit, and said control circuit is responsive to said first logic state generated at said comparator output terminal to stop incrementing said memory address counter.

Claim 11

reading the instruction out of said other memory location and storing it in said first temporary storage;

Claim 12

reading the instruction out of said other memory location and storing it in said first temporary storage;

Claim 13

loading said instruction in said second temporary storage into said read-write memory at said other memory location; and

Claim 14

loading said instruction in said second temporary storage into said read-write memory at said other memory location; and

Claim 15

In a program loader for a programmable controller having a read-write memory which stores at memory locations instructions that comprise a controller program, a method of shifting the memory location of a set of said instructions, the steps comprising:

Claim 16

In a program loader for a programmable controller having a read-write memory which stores at memory locations instructions that comprise a controller program, a method of shifting the memory location of a set of said instructions, the steps comprising:

Claim 17

repeating steps 2, 3, 4 and 5 until said entire set of instructions has been shifted.

Claim 18

repeating steps 2, 3, 4 and 5 until said entire set of instructions has been shifted.

Claim 19

In a program loader having means for loading the instructions of a controller program into a read-write memory of a programmable controller, the improvement comprising first editing means for shifting the memory location of a set of said controller program instructions, said first editing means including: a memory address counter having an address input terminal and an output terminal, said memory address counter output terminal being connectable to the address terminals on said read-write memory and said memory address counter being operable when enabled to sequentially address the memory locations of controller program instructions; a memory address input circuit connected to said address input terminal on said memory address counter to address a selected memory location; a first temporary storage having an output terminal and an input terminal, said input terminal being connectable to a data output terminal on said read-write memory to receive the controller program instructions read therefrom; and a second temporary storage having an input terminal connected to the output terminal of said first temporary storage to receive a controller program instruction therefrom and an output terminal connectable to the data input terminal on said read-write memory to load a controller program instruction into an addressed memory location in said read-write memory; wherein said first editing means is operable to sequentially shift the memory location of each instruction in said set of controller program instructions by leading each out of said read-write memory to said first temporary storage, transferring each to said second temporary storage, and then loading each back into said read-write memory at a different memory location.

Claim 20

In a program loader having means for loading the instructions of a controller program into a read-write memory of a programmable controller, the improvement comprising first editing means for shifting the memory location of a set of said controller program instructions, said first editing means including: a memory address counter having an address input terminal and an output terminal, said memory address counter output terminal being connectable to the address terminals on said read-write memory and said memory address counter being operable when enabled to sequentially address the memory locations of controller program instructions; a memory address input circuit connected to said address input terminal on said memory address counter to address a selected memory location; a first temporary storage having an output terminal and an input terminal, said input terminal being connectable to a data output terminal on said read-write memory to receive the controller program instructions read therefrom; and a second temporary storage having an input terminal connected to the output terminal of said first temporary storage to receive a controller program instruction therefrom and an output terminal connectable to the data input terminal on said read-write memory to load a controller program instruction into an addressed memory location in said read-write memory; wherein said first editing means is operable to sequentially shift the memory location of each instruction in said set of controller program instructions by leading each out of said read-write memory to said first temporary storage, transferring each to said second temporary storage, and then loading each back into said read-write memory at a different memory location.

Claim 21

A program loader as recited in claim 6 which includes second editing means for indicating the memory location of a selected controller program instruction, said second editing means including; an input circuit adapted to generate said selected controller program instruction at an output terminal; a comparator circuit having a first input terminal connectable to receive the controller program instructions read out of said read-write memory and a second input terminal connected to said input circuit output terminal to receive said selected controller program instruction; and a memory address display circuit connected to the address input terminal of said read-write memory and being operable to display the identity of the memory location being addressed by said memory address counter when the controller program instruction applied to the first comparator input terminal is identical to said selected controller program instruction applied to the second comparator input terminal.

Claim 22

The program loader as recited in claim 7 which includes an address comparator having a first input terminal connected to the output of said memory address counter and a second input terminal connected to the output of said memory address input circuit, said address comparator being operable to disable said memory address counter when the memory address generated thereby is identical to that generated by said memory address input circuit.

Claim 23

The program loader as recited in claim 8 which includes a data input selector having a first input terminal connected to said input circuit output terminal, a second input terminal connected to the output terminal on said second temporary storage and an output terminal connectable to said read-write memory data input terminal.

Claim 24

The program loader as recited in claim 9 in which the editing functions are controlled by a polyphase clock pulse generator having a plurality of output terminals and a set of logic gates each logic gate having an input terminal connected to one of said clock pulse generator output terminals, and in which selected logic gate output terminals connect to said first temporary storage, said second temporary storage, said memory address counter and said comparator circuit.