Abstract A processor system having a main memory to store user instructions and a read only memory which contains microroutines to emulate the user instructions. A user''s instruction is fetched from the main memory and placed in an instruction register, a separate decode read only memory holds the individual starting address for the appropriate microroutine utilized in a current user instruction. The operation code of the user''s instruction is applied from the instruction register to the decode read only memory for obtaining the starting address of a predetermined microroutine. Further, multiplication and division are performed according to a unique set of microroutines to significantly decrease processor operating time.
A method for performing user''s instructions which are stored in a main memory of a processor in accordance with microroutines built into a first read only memory and starting addresses built into a second, read only memory, comprising the steps of fetching a user''s instruction from said main memory; initiating a phase placing said user''s instruction in an instruction register; applying the operation code of said user''s instruction from said instruction register to said second read only memory for obtaining a starting address for a predetermined microroutine from the first read only memory each individual starting address wired into the second read only memory addressing its own particular one of said built in microroutines; accessing by the obtained starting address the particular microroutine in the first read only memory which will execute the fetched user''s instruction; and causing said processor to process the accessed microroutine in compliance with said user''s instructions.
Claim 2
Independent Claim
151 words
A method for performing user''s instructions which are stored in a main memory of a processor in accordance with microroutines built into a first read only memory and starting addresses built into a second, read only memory, comprising the steps of fetching a user''s instruction from said main memory; initiating a phase placing said user''s instruction in an instruction register; applying the operation code of said user''s instruction from said instruction register to said second read only memory for obtaining a starting address for a predetermined microroutine from the first read only memory each individual starting address wired into the second read only memory addressing its own particular one of said built in microroutines; accessing by the obtained starting address the particular microroutine in the first read only memory which will execute the fetched user''s instruction; and causing said processor to process the accessed microroutine in compliance with said user''s instructions.
Claim 3
Dependent Claim
31 words
The method of claim 1 in which there is provided the further step of fetching the next user''s instruction from the main memory after the present user''s instruction has been executed.