Patent US3813525A successfully refreshed from Google Patents.
← Back to Patent Explorer
US3813525A Expired / Lapsed US ⏱️ 0.0 years remaining

Counter and preset unit

Assignee: Hersey Products Inc
•
Filing: 1972-05-30
•
Granted: 1974-05-28
•
Expires: 1992-05-30
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A counting system including a solid state counter and preset unit which counts an input pulse signal and compares it in a logic gating circuit with a preset number, a display device which permits the displaying of either the preset number or the incoming count and interlocking means to prevent accidental disruption of a count sequence.

Inventors

  • 👤 R Kitterman
  • 👤 G Giles

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-22 21:59
CPC Classifications
G; G06; G06M; G06M3/00; G06M3/02

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 177 words
A solid state preset counter circuit comprising means for inserting a preset count into said circuit, incoming signal counter means, comparator circuit means for comparing the preset count and incoming signal count, output circuit means for producing a utilization signal when a comparison is made, isolation means for isolating and preventing operation of said preset counter circuit when said incoming signal counter means is counting, display means for selectively providing a visual display of either the preset count or incoming signal count, and display switching means for switching said display means between said preset count and incoming signal count circuits, said means for inserting a preset count further comprising a preset count circuit having a preset count switch means, preset counter means, reset means and gating means adapted to be enabled by a signal from said comparator upon the completion of a count sequence, whereby actuation of said reset means by said display switching means and enabling of said gating means completes said preset count circuit to permit setting of a preset count in said preset counter.
Claim 2
Dependent Claim 177 words
A solid state preset counter circuit comprising means for inserting a preset count into said circuit, incoming signal counter means, comparator circuit means for comparing the preset count and incoming signal count, output circuit means for producing a utilization signal when a comparison is made, isolation means for isolating and preventing operation of said preset counter circuit when said incoming signal counter means is counting, display means for selectively providing a visual display of either the preset count or incoming signal count, and display switching means for switching said display means between said preset count and incoming signal count circuits, said means for inserting a preset count further comprising a preset count circuit having a preset count switch means, preset counter means, reset means and gating means adapted to be enabled by a signal from said comparator upon the completion of a count sequence, whereby actuation of said reset means by said display switching means and enabling of said gating means completes said preset count circuit to permit setting of a preset count in said preset counter.
Claim 3
Dependent Claim 18 words
The counter of claim 1 further including a stop switch adapted to enable said gating means upon actuation.
Claim 4
Dependent Claim 153 words
A counting system for comparing a preset count with a monitored count comprising input switch means for inserting a preset count into the system, first counter means to receive said preset count, second counter means for counting input signals from a monitored device, comparator circuit means for comparing said preset count with said monitored count, means coupled to said comparator means to provide a utilization signal when a comparison is made between said preset and monitored counts, count display means including means for selectively displaying either said preset or monitored counts and means for preventing accidental interruption of an initiated counting sequence including means for isolating said counter circuits from said input means and means for interlocking said counters until a comparison is made, said interlocking means including a first reset means providing a reset signal to said second counter and a second reset means providing a reset signal to said first counter.
Claim 5
Dependent Claim 153 words
A counting system for comparing a preset count with a monitored count comprising input switch means for inserting a preset count into the system, first counter means to receive said preset count, second counter means for counting input signals from a monitored device, comparator circuit means for comparing said preset count with said monitored count, means coupled to said comparator means to provide a utilization signal when a comparison is made between said preset and monitored counts, count display means including means for selectively displaying either said preset or monitored counts and means for preventing accidental interruption of an initiated counting sequence including means for isolating said counter circuits from said input means and means for interlocking said counters until a comparison is made, said interlocking means including a first reset means providing a reset signal to said second counter and a second reset means providing a reset signal to said first counter.
Claim 6
Dependent Claim 32 words
The counting system of claim 3 wherein said interlocking means further comprises a start circuit which provides an enabling pulse to permit said first and second counters to begin a counting sequence.
Claim 7
Dependent Claim 57 words
The counting system of claim 4 wherein said interlocking means includes means for disabling said first counter during the start or counting mode to prevent a change in the preset count input, said disabling means further including a gating means and said display switch means, when said display switch means is in the monitored count display position.
Claim 8
Dependent Claim 44 words
The counting system of claim 5 wherein said interlocking means including a stop circuit and a reset switch wherein said stop circuit must be enabled in order to complete the circuit to said reset switch to enable said reset switch to its operative position.

References Cited (Backward Citations)

US2928033A Cited
US3272970A Cited
US3323527A Cited
US3441719A Cited
US3490017A Cited
US3580421A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-05-27 1977-11-26 1978-05-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-05-27 1981-11-26 1982-05-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-05-27 1985-11-26 1986-05-28 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag