Multithreshold analog to digital converter

Claim 2

Apparatus for converting an analog input signal into multiple bit binary digital output code and comprising circuitry for comparing said analog input signal relative to upper and lower threshold signal levels associated with a predetermined bit position in the output digital code, said circuitry comprising, first and second differential transistor pairs each having first and second transistor stages including base, collector and emitter elements, the base of one of said transistors of each pair being connected to said analog input signal, the base of the other transistor in said first pair being connected to a first biasing voltage defining said lower threshold signal level and the base of the other transistor in said second pair being connected to a second biasing voltage defining said upper threshold signal level, the emitters of the transistors in each pair being connected together, the collector of said one transistor of said first pair being connected to a common junction with the collector of said other transistor of said second pair, an output transistor stage having base, emitter and collector elements, said output transistor stage being effective depending upon its collector-emitter conduction state of producing a signal representing a binary output bit, and a diode interconnecting the base of said output transistor stage to the common junction of the collectors of said one transistor of said first pair and said other transistor of said second pair, said diode becoming biased to change the conduction state of said output transistor stage when the analog input signal is greater than the lower signal level defined by said first biasing voltage and less than the upper signal level defined by said second signal level.

Claim 3

An analog-to-digital conversion apparatus wherein there is one first and one second differential transistor pair for detecting the value of an analog input signal relative to an associated pair of upper and lower threshold levels and wherein each of said first and second differential transistor pairs comprises first and second transistor stages having base, collector and emitter elements, the base of one of said transistors of each pair being connected to said analog input signal, the base of the other transistor in said first pair being connected to a first biasing voltage defining said lower threshold signal level and the base of the other transistor in said second pair being connected to a second biasing voltage defining said upper threshold signal level, the emitters of the transistors in each pair being connected together, first isolation circuit means connecting the collector of said one transistor of said first pair and the collector of said other transistor of said second pair to a first common junction, second isolation circuit means connecting the collector of said other transistor of said second pair and the collector of said one transistor of any other transistor pair having an associated threshold level to a second common junction, first and second output transistor stages associated with different binary output bit positions and each having a base, emitter and collector elements and each being effective depending upon its collector-emitter conduction state of producing a signal representing a binary output bit in the associated bit position, and first and second diode interconnecting the bases of each of said first and second output transistor stages to said first and second common junctions respectively, each of said first and second diodes becoming biased to change the conduction state of said first and second output transistor stages respectively to be such that a binary output bit occurs only when the analog input signal lies between the associated pair of upper and lower threshold levels.

Claim 4

An analog-to-digital conversion apparatus wherein there is one first and one second differential transistor pair for detecting the value of an analog input signal relative to an associated pair of upper and lower threshold levels and wherein each of said first and second differential transistor pairs comprises first and second transistor stages having base, collector and emitter elements, the base of one of said transistors of each pair being connected to said analog input signal, the base of the other transistor in said first pair being connected to a first biasing voltage defining said lower threshold signal level and the base of the other transistor in said second pair being connected to a second biasing voltage defining said upper threshold signal level, the emitters of the transistors in each pair being connected together, first isolation circuit means connecting the collector of said one transistor of said first pair and the collector of said other transistor of said second pair to a first common junction, second isolation circuit means connecting the collector of said other transistor of said second pair and the collector of said one transistor of any other transistor pair having an associated threshold level to a second common junction, first and second output transistor stages associated with different binary output bit positions and each having a base, emitter and collector elements and each being effective depending upon its collector-emitter conduction state of producing a signal representing a binary output bit in the associated bit position, and first and second diode interconnecting the bases of each of said first and second output transistor stages to said first and second common junctions respectively, each of said first and second diodes becoming biased to change the conduction state of said first and second output transistor stages respectively to be such that a binary output bit occurs only when the analog input signal lies between the associated pair of upper and lower threshold levels.