US3801880A
Expired / Lapsed
US
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Multilayer interconnected structure for semiconductor integrated circuit and process for manufacturing the same
Assignee: Hitachi Ltd
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Filing: 1972-09-11
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Granted: 1974-04-02
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Expires: 1992-09-11
Abstract
Abstract A multilayer interconnected structure is composed of a first patterned layer formed on a semiconductor substrate, through an SiO2 film where necessary, lands, trapezoidal in cross section, which are formed on the first patterned layer to connect the latter to another patterned layer to be formed thereon, a thermosetting polymer layer applied on the first layer to a thickness up to the surface of the trapezoidal lands, and a second patterned layer spread over the resin layer and electrically connected to the trapezoidal lands. By this fabrication technique a multilayer interconnected structure is obtained which has a minimum of steps in its individual patterned layers and possesses desirable inter-layer insulation characteristics.
Inventors
- 👤 S Harada
- 👤 S Nonogaki
- 👤 Y Oba
- 👤 T Kohashi
- 👤 K Sato
- 👤 A Saiki
- 👤 T Okabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 14:30
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/68; H10P14/683; H10P14/40; H10P14/412; H10P14/69; H10P14/6903; H10P95/00; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/063; H10W20/0633; H10W20/069; H10W20/0693; H10W74/00; H10W74/40; H10W74/43; Y; Y10; Y10T; Y10T428/00; Y10T428/24; Y10T428/24273; Y10T428/24322; Y10T428/24331; Y10T428/24802; Y10T428/24851; Y10T428/24917
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
199 words
A multilayer interconnected structure comprising: a semiconductor substrate; a first layer of insulating material selectively disposed on a major surface of said substrate while exposing predetermined surface areas of said major surface through apertures therein; a first conductive layer formed with a first prescribed pattern over selected portions of the surface of said first layer of insulating material, said first conduCtive layer including spaced apart trapezoidally shaped land portions disposed directly on said first layer insulating of insulating material; a second conductive layer formed with a second prescribed pattern over prescribed portions of the surface of said first layer of insulating material, extending through said aperture and contacting said major surface of said substrate and being disposed on said tranezoidally-shaped land portions of said first conductive layer so as to extend onto the upper surfaces thereof; and a second layer of insulating material consisting of a dielectric layer covering said first layer of insulating material and having embedded therein said first and second conductive layers in a manner to be substantially flush with the upper surface of the portions of said second conductive layer on the upper surfaces of said trapezoidally shaped land portions of said first conductive layer.
Claim 2
Dependent Claim
15 words
A multilayer interconnected structure according to claim 2, wherein said first conductive layer is aluminum.
Claim 3
Dependent Claim
15 words
A multilayer interconnected structure according to claim 3, wherein said second conductive layer is aluminum.
Claim 4
Dependent Claim
35 words
A multilayer interconnected structure according to claim 1, wherein said dielectric layer consists of a thermosetting polymer resin selected from the group consisting of epoxy resin, phenol resin, polycarbonate resin, polyamide resin, and polybenzimidazole resin.
Claim 5
Dependent Claim
35 words
A multilayer interconnected structure according to claim 2, wherein said dielectric layer consists of a thermosetting polymer resin selected from the group consisting of epoxy resin, phenol resin, polycarbonate resin, polyamide resin, and polybenzimidazole resin.
Claim 6
Dependent Claim
60 words
A multilayer interconnected structure according to claim 1, wherein the substrate is a semiconductor plate formed with a plurality of circuit elements, such as a transistor and a diode, in the surface portion, and the first conductive layer is partly connected electrically to the electrodes of the circuit elements, so that suitable electrical circuits are formed among the circuit elements.
Claim 7
Dependent Claim
32 words
A multilayer interconnected structure according to claim 1, wherein the first conductive layer is formed of a metal selected from the group consisting of aluminum, gold, molybdenum, chromium, nickel, platinum, and titanium.
Claim 8
Dependent Claim
41 words
A multilayer interconnected structure according to claim 1, wherein the first conductive layer is formed of an alloy made of a combination of two or more metals selected from the group consisting of aluminum, gold, molybdenum, chromium, nickel, platinum, and titanium.
Claim 9
Dependent Claim
41 words
A multilayer interconnected structure according to claim 1, further comprising a second conductive layer, formed with a second prescribed pattern on said first dielectric layer and contacting at least one selected one of said at least one trapezoidally shaped land portion.
Claim 10
Dependent Claim
42 words
A multilayer interconnected structure according to claim 2, wherein said substrate is a semiconductor plate formed with a plurality of circuit elements in the surface portion thereof and said first conductive layer is at least partially connected electrically to said circuit elements.
Claim 11
Dependent Claim
146 words
A process for manufacturing a multilayer interconnected structure for a semiconductor integrated circuit comprising the steps of: a. forming a first patterned conductive layer with a desired pattern over a substrate surface; b. coating the first patterned conductive layer with a metallic conductive layer and then selectively removing the latter layer thereby forming metallic lands, trapezoidal in cross section, of said metallic layer at desired points over the first patterned layer; c. forming a dielectric layer around the trapezoidal metallic lands to a height substantially flush with the upper ends of said lands; d. removing the dielectric film so formed in step c so as to thinly cover the upper portions of said trapezoidal metallic lands, and e. forming a second patterned conductive layer with a desired pattern iN electrical contact with the upper portions of the trapezoidal metallic lands and spread over the dielectric layer.
Claim 12
Dependent Claim
39 words
A process according to claim 12, wherein the first patterned conductive layer is so formed that, after the trapezoidal metallic lands have been formed over the substrate surface, the first layer is in electrical contact with said metallic lands.
Claim 13
Dependent Claim
15 words
A process according to claim 12, wherein the dielectric consists of a thermosetting polymer resin.
Claim 14
Dependent Claim
14 words
A process according to claim 12, wherein the dielectric consists of a vitreous film.
Claim 15
Dependent Claim
40 words
A process according to claim 12, wherein steps a and b have an intermediate step of forming a film of a metal selected from the group consisting of molybdenum, chromium, nickel, copper, and gold, over the first patterned conductive layer.
Claim 16
Dependent Claim
29 words
A method according to claim 12, wherein the conductor to be patterned is a metal selected from the group consisting of aluminum, gold, molybdenum, chromium, nickel, platinum, and titanium.
Claim 17
Dependent Claim
50 words
A process according to claim 12, wherein the conductor to be patterned is an alloy combining two or more metals selected from the group consisting of aluminum, gold, molybdenum, chromium, nickel, platinum, and titanium, or a multiple film consisting of two or more layers of such an alloy or alloys.
Claim 18
Dependent Claim
27 words
A process according to claim 12, wherein the metal or alloy forming the conductor to be patterned is dissimilar to the one constituting the trapezoidal metallic lands.
Claim 19
Dependent Claim
180 words
A process for manufacturing a multilayer interconnected structure for a semiconductor integrated circuit comprising the steps of: a. coating a substrate surface with a metallic conductive layer and then removing the portions of the metallic conductive layer other than the portions of a desired pattern selectively to a predetermined depth which is less then the thickness of the coated metallic conductive layer; b. selectively removing said conductive layer in certain portions to a sufficient depth to permit insulation of said conductive layer, thereby forming trapezoidal lands of said metallic conductor in certain portions of said conductive layer and also forming a first patterned conductive layer; c. forming a dielectric layer around the trapezoidal metallic lands to a height substantially flush with the upper ends of said lands; d. removing the dielectric film so formed in step c so as to thinly cover the upper portions of said trapezoidal metallic lands, and e. forming a second patterned conductive layer with a desired pattern in electrical contact with the upper portions of the trapezoidal metallic lands and spread over the dielectric layer.
Claim 20
Dependent Claim
157 words
A process for manufacturing a multilayer interconnected structure for a semiconductor integrated circuit comprising the steps of: a. coating a substrate surface with a metallic conductive layer and then selectively removing said conductive layer to a predetermined depth, thereby forming trapezoidal metallic lands of said metallic conductor in certain portions of said conductive layer; b. further selectively removing said conductive layer to a desired depth, thereby forming a first conductive layer with a desired pattern in certain portions of said conductive layer; c. forming a dielectric layer around the trapezoidal metallic lands to a height substantially flush with the upper ends of said lands; d. removing the dielectric film so formed in step c so as to thinly cover the upper portions of said trapezoidal metallic lands, and e. forming a second patterned conductive layer with a desired pattern in electrical contact with the upper portions of the trapezoidal metallic lands and spread over the dielectric layer.
Claim 21
Dependent Claim
192 words
A process for manufacturing a multilayer interconnected structure for a semiconductor integrated circuit comprising the steps of: a. forming an insulating layer on a substrate surface; b. removing predetermined portions of the insulating layer so as to expose predetermined portions oF the substrate surface; c. coating a metallic conductive layer on the insulating layer and the exposed portions of the substrate surface; d. removing the metallic conductive layer so as to form metallic lands, trapezoidal in cross section, of the metallic layer at desired points on the insulating layer; e. coating a first patterned conductive layer with a desired pattern over the substrate surface, the insulating layer and the trapezoidal metallic lands; f. forming a dielectric layer consisting of a thermosetting polymer resin around the trapezoidal metallic lands to a height substantially flush with the upper ends of said lands: g. removing the dielectric film so formed in step f as to thinly cover the upper portion of said trapezoidal metallic lands; and h. forming a second patterned conductive layer with a predetermined pattern in electrical contact with the upper portions of the trapezoidal metallic lands and spread over the dielectric layer.
Claim 22
Dependent Claim
16 words
A multilayer interconnected structure according to claim 1, wherein said dielectric layer consists of polyimide resin.
Claim 23
Dependent Claim
16 words
A multilayer interconnected structure according to claim 2, wherein said dielectric layer consists of polyimide resin.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-04-01 | 1977-10-01 | 1978-04-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-04-01 | 1981-10-01 | 1982-04-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-04-01 | 1985-10-01 | 1986-04-02 | $7700.00 | Window Closed / Lapsed |