Automatic memory test and correction system

Claim 2

In a data processing system having a memory for storing data, the improvement comprising: tape reading means for transferring data from a tape to said memory, comparing means for comparing data stored in said memory with data on said tape and for signaling the presence of any discrepancy, means connected to said comparing means for correcting said discrepancy, said correcting means including manual means and automatic means connected to said manual means for correcting said discrepancy, an address counter connected to said memory for monitoring said memory, an address readout for indicating the state of said counter, input readout means for displaying data being read into said memory, output readout means for displaying data being read out of said memory, an input data register for temporary storage of input data for said memory, an output data register for temporary storage of output data from said memory, a pulse generator for driving said system, an input switching and manual loading circuit for forwarding data to said input data register from said tape reading means, a logic circuit for controlling said system, said input readout means being connected to said tape readout means through said input switching and manual loading circuit, said output readout means being connected to said output data register to display the data from said memory stored in said output data register.

Claim 3

The apparatus of claim 1 and including means connecting said tape reader to said input switching and manual loading means for forwarding data from said tape reader to said input switching and manual loading means, comparator connecting means enabling said comparing means to compare memory output data temporarily stored in said output data register with input data from said tape reader and said input switching and manual loading circuit, and for signaling the presence of any discrepancy to said logic circuit, said logic circuit comprising: gatinG means for passing a pulse from said pulse generator to step said tape reader and to initiate a cycle in said memory, a first flipflop responsive to said comparator and a second flipflop responsive to said tape reader for controlling said gating means, a third flipflop responsive to an error-correct switch to initiate pulses to initiate a cycle of said memory, step said address counter down, and to switch said memory to a write mode.

Claim 4

The apparatus of claim 2, said logic circuit comprising: a flipflop 38 connected to be set by an output from said comparison means 18 and by a continue-test switch 28, an AND gate 36 connected to be enabled by a set output from flipflop 38 to pass a pulse from said pulse generator 1, an AND gate 40, a flipflop 42 connected to be set by a start-command pulse and to be reset by a stop-command pulse from said tape reader 1, an enabling connection from the set output of flipflop 42 to an input of AND gate 40 enabling AND gate 40 to pass an output pulse from said AND gate 36, a reset connection from the output of AND gate 40 to flipflop 38, an OR gate 44 connected to pass an output pulse from AND gate 40 to initiate a cycle of said memory 6, a connection from the output of AND gate 36 to said tape reader 1, a flipflop 46, an error correct switch 30 connected to trigger said flipflop 46, a one-shot 48 connected to be triggered by an output from flipflop 46, a one-shot 50 connected to be triggered by the leading edge of an output pulse from one-shot 48, a one-shot 52 connected to be triggered by the trailing edge of an output pulse from one-shot 48, an OR gate 54 connected to pass the output pulses of one-shots 50 and 52 to said address counter 20, a flipflop 56 connected to be set by the leading edge of an output pulse from one-shot 48 and to be reset by the trailing edge of an output pulse from one-shot 48, a connection from the set output of flipflop 56 to forward a write command to memory 6, a connection from the reset output of flipflop 56 to forward a read command to memory 6, and a connection from the output of OR gate 54 to an input of OR gate 44 to pass the output pulses of one-shots 50 and 52 to said memory 6.

Claim 5

The apparatus of claim 3, said input switching and loading circuit comprising: a flipflop 60, a switch 70 connected to set said flipflop 60, a control flipflop 62 connected to be reset by an output pulse from said comparing means, a clear-input switch 26 connected to reset said flipflop 60 and to set said control flipflop 62, an AND gate 69, a connection from a first output of said flipflop 62 to a first input of said AND gate 68, a connection from an output of said flipflop 60 to a second input of said AND gate 68, an AND gate 64, a connection from a second output of said control flipflop 62 to a first input of said AND gate 64, a connection from an output of said tape reader to a second input of said AND gate 64, an OR gate 66, a connection from the output of said AND gate 68 to a first input of said OR gate 66, a connection from the output of said AND gate 64 to a second input of said OR gate 66, a connection from the output of said OR gate 66 to an input of said comparing means and to an input of said input data register, and a connection between the output of said OR gate 66 and said switch 70, whereby the control flipflop 62 may be set to pass data from switch 70 to said comparison means 18 and to said input data register 8, and to inhibit data from said tape reading means 2, and may be reset to pass data from said tape reading means 2 and to inhibit data from said switch 70.

Claim 6

The apparatus of claim 4, said input switching and loading circuit comprising: a plurality of switches 70, a like plurality of flipflops 60, a like plurality of gates 64, a like plurality of gates 66, aNd a like plurality of gates 68 all connected as described in claim 7 to form a like plurality of discrete circuits for switching and loading, all of said circuits being connected to clear-input switch 26 and control flipflop 62 in the manner described in claim 7.