Digital counter and timer with multiplex setting and readout

Claim 2

A digital counter adapted to count down from a selected decimal number having at least two selected digits, the first digit being the lesser significant and the second digit being the more significant, said counter comprising: a. first and second binary down counter means connected in cascade with the first counter means including means for setting therein a first binary coded representation of said first digit, said second counter means including means for setting therein a second binary coded representation of said second digit and means for inhibiting said two setting means upon creation of a blocking signal; b. said first counter means including means responsive to input pulses for counting down from said first set binary coded representation in digital increments to a zero count and means for then successively counting down from a binary coded representation of the digit nine to a zero count; c. said second counter means including means responsive to each zero count of said first counter means for counting down from said second binary coded representation in digital increments to a zero count; d. means responsive to a zero count in both of said digital counter means for producing an output from said digital counter, said zero counts coming when the number of input pulses corresponds to the selected decimal number; e. said first counter means including a first group of output leads carrying binary logic representative of the decimal digit of said first counter means at any given time; f. said second counter means including a second group of output leads carrying binary logic representative of the decimal digit of said second counter means at any given time; g. first digit readout means for displaying a selected decimal digit upon receipt of binary logic representative of such decimal digit, said first readout means having a first input means for receiving binary logic representative of a decimal digit and a second input means for activating said first readout means; h. second digit readout means for displaying a selected decimal digit upon receipt of binary logic representative of such decimal digit, said second readout means having a first input means for receiving binary logic representative of a decimal digit and a second input means for activating said second readout means; i. means for creating a succession of first and second signals; j. means responsive to creation of said first signal for connecting said first group of output leads to said first input means of both of said first and said second digit readout means and for simultaneously energizing only said second input means of said first digit readout means whereby said first signal causes said first readout means to display the digit of said first counter means at any given time; k. means responsive to creation of said second signal for connecting said second group of output leads to said first input means of both of said first and second digit readout means and for simultaneously energizing only said second input means of said second digit readout means whereby said second signal causes said second readout means to display the digit of said second counter means at any given time; l. means for applying a pulsing signal to said first counter means when said blocking signal is created; and, m. means for selectively creating said blocking signal whereby said counter means can count down from said binary coded representation.

Claim 3

A digital counter as defined in claim 1 including a source of a known clocking pulse signal and means for connecting said clocking pulse signal to said means for applying pulsing signal to saId first counter means whereby said digital counter operates as a timer.

Claim 4

A digital counter as defined in claim 1 wherein said first input means of both of said first and second readout means are connected to a common third group of leads with each lead of said third group of leads having a first switching means for connecting said each lead of said third group to a lead of said first group of output leads and a second switching means for connecting said each lead to a lead of said second group of output leads, said first switching means being closed in response to creation of said first signal and said second switching means being closed in response to creation of said second signal.

Claim 5

A digital counter as defined in claim 3 wherein said first and second switching means are logic switching means.

Claim 6

A digital counter as defined in claim 4 wherein said first and second switching means are AND gates each having a first logic input connected to a lead from one of said first and second group of output leads and a second logic input connected to a source of one of said first or second signals.

Claim 7

A digital counter as defined in claim 1 including a first manually codable device for creating a first binary coded logic corresponding to said first selected decimal digit, a second manually codable device for creating a second binary coded logic corresponding to said second selected decimal digit, means for transferring said first coded logic into said first counter means and means for transferring said second coded logic into said second counter means.

Claim 8

A digital counter as defined in claim 6 wherein said first and second codable devices each include a plurality of electrical branches with each branch including a manually actuated switch and a diode with each branch corresponding to a first binary logic when said switch is closed and a second binary logic when said switch is opened.

Claim 9

A digital counter as defined in claim 6 wherein said first and second codable devices have an energizing input lead and each of said transferring means includes a group of leads extending from said respective codable devices, a group of setting leads with said group of leads from both of said codable devices being connected to said setting leads, means for connecting said group of setting leads to said setting means of both said first and said second counter means and means responsive to creation of said first signal for energizing said energizing lead of said first codable device and for simultaneously blocking said setting means of said second counter means, means responsive to creation of said second signal for energizing said energizing lead of said second codable device and for simultaneously blocking the setting means of said first counter means whereby said first and second counter means are set to the first and second binary codes, repsectively.

Claim 10

A digital counter adapted to count down from a selected decimal number having at least two selected digits, the first digit being the lesser significant and the second digit being the more significant, said counter comprising: a. fist and second binary down counter means connected to cascade with the first counter means including means for setting therein a first binary coded representation of said first digit and said second counter means including means for setting therein a second binary coded representation of said second digit; b. said first counter means including means responsive to input pulses for counting down from said first set binary coded representation in digital increments to a zero count and means for then successively counting down from a binary coded representation of the digit nine to a zero count; c. said second counter means including means responsive to each zero count of said first counter means for counting down from said second binary coded representation in digital increments to a zero count; d. mean responsive to a zero count in both of said digital counter means for producing an ouTput from said digital counter, said zero counts coming when the number of input pulses corresponds to the selected decimal number; e. said first counter means including a first group of output leads carrying binary logic representative of the decimal digit of said first counter means at any given time; f. said second counter means including a second group of output leads carrying binary logic representative of the decimal digit of said second counter means at any given time; g. first digit readout means for displaying a selected decimal digit upon receipt of binary logic representative of such decimal digit, said first readout means having a first input means for receiving binary logic representative of a decimal digit and a second input means for activating said first readout means; h. second digit readout means for displaying a selected decimal digit upon receipt of binary logic representative of such decimal digit, said second readout means having a first input means for receiving binary logic representative of a decimal digit and a second input means for activating said second readout means; i. means for creating a succession of first and second signals; j. means responsive to creation of said first signal for connecting said first group of output leads to said first input means of both of said first and said second digit readout means and for simultaneously energizing only said second input means of said first digit readout means whereby said first signal causes said first readout means to display the digit of said first counter means at any given time; k. means responsive to creation of said second signal for connecting said second group of output leads to said first input means of both of said first and said second digit readout means and for simultaneously energizing only said second input means of said second digit readout means whereby said second signal causes said second readout means to display the digit of said second counter means at any given time; l. means for applying a plusing signal to said first counter means; m. a first manually codable device for creating a first binary coded logic corresponding to said first selected decimal digit, a second manually codable device for creating a second binary coded logic corresponding to said second selected decimal digit, means for transferring said first coded logic into said first counter means and means for transferring said second coded logic into said second counter means; n. said first and second codable devices have an energizing input lead and each of said transferring means includes a group of leads extending from said respective codable devices, a group of setting leads with said group of leads from both of said codable devices being connected to said setting leads, means for connecting said group of setting leads to said setting means of both said first and said second counter means and means responsive to creation of said fist signal for energizing said energizing lead of said first codable device and for simultaneously blocking said setting means of said second counter means, means responsive to creation of said second signal for energizing said energizing lead of said second codable device and for simultaneously blocking the setting means of said first counter means whereby said first and second counter means are set to the first and second binary codes, respectively; and, o. counter blocking means for blocking both of said setting means of said first and said second counter means after said counter means are both set with said binary codes.

Claim 11

A digital counter adapted to count down from a selected decimal number having at least two selected digits, the first digit being the lesser significant and the second digit being the more significant, said counter comprising: a. fist and second binary down counter means connected to cascade with the first counter means including means for setting therein a first binary coded representation of said first digit and said second counter means including means for setting therein a second binary coded representation of said second digit; b. said first counter means including means responsive to input pulses for counting down from said first set binary coded representation in digital increments to a zero count and means for then successively counting down from a binary coded representation of the digit nine to a zero count; c. said second counter means including means responsive to each zero count of said first counter means for counting down from said second binary coded representation in digital increments to a zero count; d. mean responsive to a zero count in both of said digital counter means for producing an ouTput from said digital counter, said zero counts coming when the number of input pulses corresponds to the selected decimal number; e. said first counter means including a first group of output leads carrying binary logic representative of the decimal digit of said first counter means at any given time; f. said second counter means including a second group of output leads carrying binary logic representative of the decimal digit of said second counter means at any given time; g. first digit readout means for displaying a selected decimal digit upon receipt of binary logic representative of such decimal digit, said first readout means having a first input means for receiving binary logic representative of a decimal digit and a second input means for activating said first readout means; h. second digit readout means for displaying a selected decimal digit upon receipt of binary logic representative of such decimal digit, said second readout means having a first input means for receiving binary logic representative of a decimal digit and a second input means for activating said second readout means; i. means for creating a succession of first and second signals; j. means responsive to creation of said first signal for connecting said first group of output leads to said first input means of both of said first and said second digit readout means and for simultaneously energizing only said second input means of said first digit readout means whereby said first signal causes said first readout means to display the digit of said first counter means at any given time; k. means responsive to creation of said second signal for connecting said second group of output leads to said first input means of both of said first and said second digit readout means and for simultaneously energizing only said second input means of said second digit readout means whereby said second signal causes said second readout means to display the digit of said second counter means at any given time; l. means for applying a plusing signal to said first counter means; m. a first manually codable device for creating a first binary coded logic corresponding to said first selected decimal digit, a second manually codable device for creating a second binary coded logic corresponding to said second selected decimal digit, means for transferring said first coded logic into said first counter means and means for transferring said second coded logic into said second counter means; n. said first and second codable devices have an energizing input lead and each of said transferring means includes a group of leads extending from said respective codable devices, a group of setting leads with said group of leads from both of said codable devices being connected to said setting leads, means for connecting said group of setting leads to said setting means of both said first and said second counter means and means responsive to creation of said fist signal for energizing said energizing lead of said first codable device and for simultaneously blocking said setting means of said second counter means, means responsive to creation of said second signal for energizing said energizing lead of said second codable device and for simultaneously blocking the setting means of said first counter means whereby said first and second counter means are set to the first and second binary codes, respectively; and, o. counter blocking means for blocking both of said setting means of said first and said second counter means after said counter means are both set with said binary codes.

Claim 12

A digital counter means as defined in claim 9 wherein said counter blocking means includes a circuit responsive to creation of said succession of first and second signal for blocking said setting means of said first and said second counter means after a set minimum time exceeding the time for creating at least one first and one second signal.

Claim 13

A digital counter as defined in claim 10 wherein said circuit includeS means for blocking said pulse applying means for a time at least as long as said minimum time.

Claim 14

A digital counter adapted to count down from a selected decimal number having at least two selected digits, the first digit being the lesser significant and the second digit being the more significant, said counter comprising: a. first and second binary down counter means connected in cascade with the first counter means including means for setting therein a first binary coded representation of said first digit and said second counter means including means for setting therein a second binary coded representation of said second digit; b. said first counter means including means responsive to input pulses for counting down from said first set binary coded representation in digital increments to a zero count and means for then successively counting down from a binary coded representation of the digit nine to a zero count; c. said second counter means including means responsive to each zero count of said first counter means for counting down from said second binary coded representation in digital increments to a zero count; d. means responsive to a zero count in both of said digital counter means for producing an output from said digital counter, said zero counts coming when the number of input pulses corresponds to the selected decimal number; e. said first counter means including a first group of output leads carrying binary logic representative of the decimal digit of said first counter means at any given time; f. said second counter means including a second group of output leads carrying binary logic representative of the decimal digit of said second counter means at any given time; g. first digit readout means for displaying a selected decimal digit upon receipt of binary logic representative of such decimal digit, said first readout means having a first input means for receiving binary logic representative of a decimal digit and a second input means for activating said first readout means; h. second digit readout means for displaying a selected decimal digit upon receipt of binary logic representative of such decimal digit, said second readout means having a first input means for receiving binary logic representative of a decimal digit and a second input means for activating said second readout means; i. means for creating a succession of first and second signals; j. means responsive to creation of said first signal for connecting said first group of output leads to said first input means of both of said first and said second digit readout means and for simultaneously energizing only said second input means of said first digit readout means whereby said first signal causes said first readout means to display the digit of said first counter means at any given time; k. means responsive to creation of said second signal for connecting said second group of output leads to said first input means of both of said first and said second digit readout means and for simultaneously energizing only said second input means of said second digit readout means whereby said second signal causes said second readout means to display the digit of said second counter means at any given time; l. means for applying a pulsing signal to said first counter means; and, m. first means for creating a first binary logic corresponding to the first decimal digit, second means for creating a second binary logic corresponding to the second decimal digit, a group of setting leads connected in parallel to the setting means of both first and second counter means, means responsive to creation of said first signal for applying said first logic to said group of setting leads and for simultaneously blocking said setting means of said second counter means, means responsive to creation of said second signal for applying said second binary logic to said group of setting leads and for simultaneously blocking said setting means of said first counter means and means for blocKing the setting means of both said first and second counter means after said first and second binary logic has been set therein.

Claim 15

A digital counter adapted to count down from a selected decimal number having at least two selected digits, the first digit being the lesser significant and the second digit being the more significant, said counter comprising: a. first and second binary down counter means connected in cascade with the first counter means including means for setting therein a first binary coded representation of said first digit and said second counter means including means for setting therein a second binary coded representation of said second digit; b. said first counter means including means responsive to input pulses for counting down from said first set binary coded representation in digital increments to a zero count and means for then successively counting down from a binary coded representation of the digit nine to a zero count; c. said second counter means including means responsive to each zero count of said first counter means for counting down from said second binary coded representation in digital increments to a zero count; d. means responsive to a zero count in both of said digital counter means for producing an output from said digital counter, said zero counts coming when the number of input pulses corresponds to the selected decimal number; e. said first counter means including a first group of output leads carrying binary logic representative of the decimal digit of said first counter means at any given time; f. said second counter means including a second group of output leads carrying binary logic representative of the decimal digit of said second counter means at any given time; g. first digit readout means for displaying a selected decimal digit upon receipt of binary logic representative of such decimal digit, said first readout means having a first input means for receiving binary logic representative of a decimal digit and a second input means for activating said first readout means; h. second digit readout means for displaying a selected decimal digit upon receipt of binary logic representative of such decimal digit, said second readout means having a first input means for receiving binary logic representative of a decimal digit and a second input means for activating said second readout means; i. means for creating a succession of first and second signals; j. means responsive to creation of said first signal for connecting said first group of output leads to said first input means of both of said first and said second digit readout means and for simultaneously energizing only said second input means of said first digit readout means whereby said first signal causes said first readout means to display the digit of said first counter means at any given time; k. means responsive to creation of said second signal for connecting said second group of output leads to said first input means of both of said first and said second digit readout means and for simultaneously energizing only said second input means of said second digit readout means whereby said second signal causes said second readout means to display the digit of said second counter means at any given time; l. means for applying a pulsing signal to said first counter means; and, m. first means for creating a first binary logic corresponding to the first decimal digit, second means for creating a second binary logic corresponding to the second decimal digit, a group of setting leads connected in parallel to the setting means of both first and second counter means, means responsive to creation of said first signal for applying said first logic to said group of setting leads and for simultaneously blocking said setting means of said second counter means, means responsive to creation of said second signal for applying said second binary logic to said group of setting leads and for simultaneously blocking said setting means of said first counter means and means for blocKing the setting means of both said first and second counter means after said first and second binary logic has been set therein.

Claim 16

A digital counter as defined in claim 12 including means for blocking said pulse applying means until said binary logics have beet set into said first and second counter means.

Claim 17

A digital counter as defined in claim 13 wherein said pulse blocking means includes a circuit means controlled by creation of said first and second signals for blocking said pulse applying means for a time exceeding the time for creating at least one first signal and one second signal.

Claim 18

A digital counter adapted to count to a selected digital number having n digits, said counter comprising: a. a binary down counter for each of said digits arranged in order of digital significance, said counters being connected in cascade from least significant digit to most significant digit whereby when a lesser significant digit counter counts down to zero the next higher significant digit counter counts down by one, each of said binary down counters including means for setting one of said selected digits thereby preparatory to down counting from said set digits; b. a separate manually-adjustable binary-codable input means for setting each of said selected digits into one of said counters, each of said codable input means having an energizing lead and a plurality of separate binary-codable parallel circuits adapted to be coded in accordance with one of said selected digits; c. each parallel circuit of said separate codable input means being connected to a common group of setting leads whereby said setting leads receive the set binary code of one of said binary-codable input means when said energizing lead of said one binary-codable input means is energized; d. said common group of setting leads being connected to said setting means of each of said binary down counters; e. means for blocking said setting means of each of said down counters; f. circuit means for creating a distinctive binary signal for each of said digits; g. means responsive to creation of each of said signals for energizing said blocking means of all counters except the counter corresponding to said digit to which said signal corresponds; and, h. means responsive to creation of each of said signals for energizing said energizing lead of said binary-codable input means corresponding to said digit to which said signal corresponds; i. means for energizing all of said blocking means after all of said counters have been set to the selected digits; and, j. means for applying a series of pulses to said binary down counters for counting down from said set selected digits.

Claim 19

A digital counter adapted to count to a selected digital number having n digits, said counter comprising: a. a binary down counter for each of said digits arranged in order of digital significance, said counters being connected in cascade from least significant digit to most significant digit whereby when a lesser significant digit counter counts down to zero the next higher significant digit counter counts down by one, each of said binary down counters including means for setting one of said selected digits thereby preparatory to down counting from said set digits; b. a separate manually-adjustable binary-codable input means for setting each of said selected digits into one of said counters, each of said codable input means having an energizing lead and a plurality of separate binary-codable parallel circuits adapted to be coded in accordance with one of said selected digits; c. each parallel circuit of said separate codable input means being connected to a common group of setting leads whereby said setting leads receive the set binary code of one of said binary-codable input means when said energizing lead of said one binary-codable input means is energized; d. said common group of setting leads being connected to said setting means of each of said binary down counters; e. means for blocking said setting means of each of said down counters; f. circuit means for creating a distinctive binary signal for each of said digits; g. means responsive to creation of each of said signals for energizing said blocking means of all counters except the counter corresponding to said digit to which said signal corresponds; and, h. means responsive to creation of each of said signals for energizing said energizing lead of said binary-codable input means corresponding to said digit to which said signal corresponds; i. means for energizing all of said blocking means after all of said counters have been set to the selected digits; and, j. means for applying a series of pulses to said binary down counters for counting down from said set selected digits.

Claim 20

A digital counter adapted to count down from a decimal number having at least two selected digits, the first being the least significant and the second being the most significant, said counter comprising: a. a binary down counter for each of said digits arranged in order of significance, said counters being connected in cascade from least significant digit to most significant digit whereby when the least significant digit counter counts to zero the most significant digit counter counts down one, said least significant digit counter including means for setting said least significant digit therein and said most significant digit counter including means for setting said most significant digit therein; b. a first manually-adjustable binary-codable input means for setting said least significant digit into said least significant digit counter, a second manually-adjustable binary-codable input means for setting said most significant digit into said most significant digit counter; c. said first input means having a first energizing lead and a plurality of separate circuits adapted to be binary-coded in accordance with said least significant digit; d. said second input means having a second energizing lead and a plurality of separate circuits adapted to be binary-coded in accOrdance with said most significant digit; e. said circuits being connected to a common group of setting leads whereby said group of setting leads receive the set binary code of one of said first and second input means; f. said common group of setting leads being connected to said setting means of both of said counter means; g. means for creating a first and a second signal in succession; h. means responsive to creation of said first signal for energizing said first energizing lead; i. means responsive to creation of said first signal for blocking said setting means of said most significant digit counter; j. means responsive to creation of said second signal for energizing said second energizing lead; k. mean responsive to creation of said second signal for blocking said setting means of said least significant digit counter; l. means for blocking said setting means of both of said counters after said counters have been set; and, m. means for applying a series of pulses to said least significant digit counters for counting down said counters from said set selected digits.

Claim 21

A digital counter adapted to count down from a decimal number having at least two selected digits, the first being the least significant and the second being the most significant, said counter comprising: a. a binary down counter for each of said digits arranged in order of significance, said counters being connected in cascade from least significant digit to most significant digit whereby when the least significant digit counter counts to zero the most significant digit counter counts down one, said least significant digit counter including means for setting said least significant digit therein and said most significant digit counter including means for setting said most significant digit therein; b. a first manually-adjustable binary-codable input means for setting said least significant digit into said least significant digit counter, a second manually-adjustable binary-codable input means for setting said most significant digit into said most significant digit counter; c. said first input means having a first energizing lead and a plurality of separate circuits adapted to be binary-coded in accordance with said least significant digit; d. said second input means having a second energizing lead and a plurality of separate circuits adapted to be binary-coded in accOrdance with said most significant digit; e. said circuits being connected to a common group of setting leads whereby said group of setting leads receive the set binary code of one of said first and second input means; f. said common group of setting leads being connected to said setting means of both of said counter means; g. means for creating a first and a second signal in succession; h. means responsive to creation of said first signal for energizing said first energizing lead; i. means responsive to creation of said first signal for blocking said setting means of said most significant digit counter; j. means responsive to creation of said second signal for energizing said second energizing lead; k. mean responsive to creation of said second signal for blocking said setting means of said least significant digit counter; l. means for blocking said setting means of both of said counters after said counters have been set; and, m. means for applying a series of pulses to said least significant digit counters for counting down said counters from said set selected digits.

Claim 22

A digital counter as defined in claim 16 wherein each of said parallel circuits includes a diode.

Claim 23

A digital counter as defined in claim 16 wherein each of said parallel circuits includes a manually operable switch.

Claim 24

A digital counter as defined in claim 16 wherein said means for creating a first and a second signal in succession comprises a set of flip-flop circuits connected together and driven by an oscillator.

Claim 25

A digital counter adapted to count down from at least two selected digits, the first being a least significant digit and the second being a most significant digit, said counter comprising: a. a first binary counter means for counting down from said first selected digit to a zero count and then counting repeatedly from nine to a zero count when receiving input pulses; b. a second binary counter means connected to said first counter means for counting down from said second selected digit one digit upon each zero count of said first counter means; c. first codable means for setting said first digit into said first counter means, said first codable means including a first energizing lead, a plurality of circuits, and means for manually setting each of said circuits between logic 1 and logic 0, and a plurality of first output lead means connected to said circuits of said first codable means for transmitting the logic of said circuits from said first codable means upon energization of said first energizing lead; d. second codable means for setting said second digit into said second counter means, said second codable means including a second energizing lead, a plurality of circuits, and means for manually setting each of said circuits of said second codable means between logic 1 and logic 0, and a plurality of second output lead means connected to said circuits of said second codable means for transmitting the logic of said circuits of said second codable means from said second codable means, uon energization of said second energizing lead; e. a group of common leads connected to both of said first and second output lead means for alternatively receiving said logic of said first and said second codable means; f. said group of common leads being connected to both of said first and said second counter means; g. each of said counter means including means for setting said counter means upon receipt of logic from said common leads and means for blocking said setting means; h. means for creating a first and a second control signal in sequence; i. means responsive to creation of said first signal for energizing said first energizing lead and for energizing said blocking means of said second counter means whereby the logic of said first codable means is set into said first counter means; j. means responsive to creation of said second signal for energizing said secoNd energizing lead and for energizing said blocking means of said first counter means whereby the logic of said second codable means is set into said second counter means; k. means for energizing the blocking means of both of said first and said second counter means after said counter means have been set; and, l. means for applying a series of pulses to said first counter means.

Claim 26

A digital counter adapted to count down from at least two selected digits, the first being a least significant digit and the second being a most significant digit, said counter comprising: a. a first binary counter means for counting down from said first selected digit to a zero count and then counting repeatedly from nine to a zero count when receiving input pulses; b. a second binary counter means connected to said first counter means for counting down from said second selected digit one digit upon each zero count of said first counter means; c. first codable means for setting said first digit into said first counter means, said first codable means including a first energizing lead, a plurality of circuits, and means for manually setting each of said circuits between logic 1 and logic 0, and a plurality of first output lead means connected to said circuits of said first codable means for transmitting the logic of said circuits from said first codable means upon energization of said first energizing lead; d. second codable means for setting said second digit into said second counter means, said second codable means including a second energizing lead, a plurality of circuits, and means for manually setting each of said circuits of said second codable means between logic 1 and logic 0, and a plurality of second output lead means connected to said circuits of said second codable means for transmitting the logic of said circuits of said second codable means from said second codable means, uon energization of said second energizing lead; e. a group of common leads connected to both of said first and second output lead means for alternatively receiving said logic of said first and said second codable means; f. said group of common leads being connected to both of said first and said second counter means; g. each of said counter means including means for setting said counter means upon receipt of logic from said common leads and means for blocking said setting means; h. means for creating a first and a second control signal in sequence; i. means responsive to creation of said first signal for energizing said first energizing lead and for energizing said blocking means of said second counter means whereby the logic of said first codable means is set into said first counter means; j. means responsive to creation of said second signal for energizing said secoNd energizing lead and for energizing said blocking means of said first counter means whereby the logic of said second codable means is set into said second counter means; k. means for energizing the blocking means of both of said first and said second counter means after said counter means have been set; and, l. means for applying a series of pulses to said first counter means.

Claim 27

A digital counter as defined in claim 20 wherein said manual setting means of each of said circuits includes a switch having an open position corresponding to a selected one of said logic 1 and logic 0 and a closed position corresponding to the other of said logic 1 and logic 0.

Claim 28

A digital counter as defined in claim 20 wherein each of said circuits includes a diode.

Claim 29

A digital counter as defined in claim 20 including a source of a known clocking pulse signal and means for connecting said clocking pulse signal to said means for applying pulses to said first binary counter means whereby said digital counter operates as a timer.

Claim 30

A digital counter for counting down from a selected first and second decimal digit with said first digit being the lesser significant and said second digit being the more significant, said counter comprising: a. first and second binary down counter means connected in cascade, means for setting said first selected digit in said first counter means, means for setting said second digit in said second counter means and means for inhibiting said two setting means upon creation of a blocking signal; b. means for applying a pulsing input signal to said first counter means for causing said first and second counter means to count down from said set condition when said blocking signal is created; c. a first group of leads connected to said first counter means and carrying a binary logic corresponding to the digit of said first counter means at any given time; d. a second group of leads connected to said second counter means and carrying a binary logic corresponding to the digit of said second counter means at any given time; e. first readout means having a first energizing lead, a decimal display unit, a first input for receiving a binary code and means for converting said binary code to a decimal number in said unit; f. second readout means having a second energizing lead, a decimal display unit, a second input for receiving a binary code and means for converting said binary code to a decimal number in said unit; g. a group of readout leads connected in parallel with said first and said second inputs of said first and second readout means; h. means for creating a succession of first and second signals; i. means responsive to creation of said first signal for connecting said first group of leads to said group of readout leads and for simultaneously energizing said first energizing lead; j. means responsive to creation of said second signal for connecting said second group of leads to said group of readout leads and for simultaneously energizing said seocnd energizing lead; and, k. means for selectively creating said blocking signal whereby said counter means can count down from said selected digits in said counter means.

Claim 31

A digital counter for counting down from a selected first and second decimal digit with said first digit being the lesser significant and said second digit being the more significant, said counter comprising: a. first and second binary down counter means connected in cascade, means for setting said first selected digit in said first counter means, means for setting said second digit in said second counter means and means for inhibiting said two setting means upon creation of a blocking signal; b. means for applying a pulsing input signal to said first counter means for causing said first and second counter means to count down from said set condition when said blocking signal is created; c. a first group of leads connected to said first counter means and carrying a binary logic corresponding to the digit of said first counter means at any given time; d. a second group of leads connected to said second counter means and carrying a binary logic corresponding to the digit of said second counter means at any given time; e. first readout means having a first energizing lead, a decimal display unit, a first input for receiving a binary code and means for converting said binary code to a decimal number in said unit; f. second readout means having a second energizing lead, a decimal display unit, a second input for receiving a binary code and means for converting said binary code to a decimal number in said unit; g. a group of readout leads connected in parallel with said first and said second inputs of said first and second readout means; h. means for creating a succession of first and second signals; i. means responsive to creation of said first signal for connecting said first group of leads to said group of readout leads and for simultaneously energizing said first energizing lead; j. means responsive to creation of said second signal for connecting said second group of leads to said group of readout leads and for simultaneously energizing said seocnd energizing lead; and, k. means for selectively creating said blocking signal whereby said counter means can count down from said selected digits in said counter means.

Claim 32

A digital counter as defined in claim 24 including a source of a known clocking pulse signal and means for connecting said clocking pulse signal to said means for applying a pulsing signal to said first counter means whereby said digital counter operates as a timer.

Claim 33

A digital counter as defined in claim 24 including a first manually codable device for creating a first binary-coded logic corresponding to said first selected decimal digit, a second manually codable device for creating a second binary-coded logic corresponding to said second selected decimal digit, means for transferring said first coded logic into said first counter means and means for transferring said second coded logic into said second counter means.

Claim 34

A digital counter as defined In claim 26 wherein said first and second codable devices each include a plurality of electrical branches with each branch including a manually-actuated switch and a diode with each branch corresponding to a first binary logic when said switch is closed and a second binary logic when said switch is opened.

Claim 35

A digital counter as defined in claim 26 wherein said first and second codable devices have an energizing input lead and each of said transferring means includes a group of leads extending from said respective codable devices, a group of setting leads with said group of leads from both of said codable devices being connected to said setting leads, means for connecting said group of setting leads to said setting means of both of said first and said second counter means and means responsive to creation of said first signal for energizing said energizing input lead of said first codable device and for simultaneously blocking said setting means of said second counter means, means responsive to creation of said second signal for energizing said energizing input lead of said second codable device and for simultaneously blocking said setting means of said first counter means whereby said first and second counter means are set to the first and second binary codes, respectively.

Claim 36

A digital counter for counting down from a selected first and second decimal digit with said first digit being the lesser significant and said second digit being the more significant, said counter comprising: a. first and second binary down counter means connected in cascade, means for setting said first selected digit in said first counter means and means for setting said second digit in said second counter means; b. means for applying a pulsing input signal to said first counter means for causing said first and second counter means to count down from said set condition; c. a first group of leads connected to said first counter means and carrying a binary logic corresponding to the digit of said first counter means at any given time; d. a second group of leads connected to said second counter means and carrying a binary logic corresponding to the digit of said second counter means at any given time; e. first readout means having a first energizing lead, a decimal display unit, a first input for receiving a binary code and means for converting said binary code to a decimal number in said unit; f. second readout means having a second energizing lead, a decimal display unit, a second input for receiving a binary code and means for converting said binary code to a decimal number in said unit; g. a group of readout leads connected in parallel with said first and said second inputs of said first and second readout means; h. means for creating a succession of first and second signals; i. means responsive to creation of said first signal for connecting said first group of leads to said group of readout leads and for simultaneously energizing said first energizing lead; j. means responsive to creation of said second signal for connecting said second group of leads to said group of readout leads and for simultaneously energizing said second energizing lead; k. a first manually codable device for creating a first binary-coded logic corresponding to said first selected decimal digit, a second manually codable device for creating a second binary-coded logic corresponding to said second selected decimal digit, means for transferring said first coded logic into said first counter means and means for transferring said second coded logic into said second counter means; l. said first and second codable devices have an energizing input lead and each of said transferring means include a group of leads extending from said respective codable devices, a group of setting leads with said group of leads from both of said codable devices being connected to said setting leads, means for connecting said group of setting leads to said setting means of both of said first and said secoNd counter means and means responsive to creation of said first signal for energizing said energizing input lead of said first codable device and for simultaneously blocking said setting means of said second counter means, means responsive to creation of said second signal for energizing said energizing input lead of said second codable device and for simultaneously blocking said setting means of said first counter means whereby said first and second counter means are set to the first and second binary codes, respectively; and, m. counter blocking means for blocking both of said setting means of said first and said second counter means after said counter means are both set with said binary codes.

Claim 37

A digital counter for counting down from a selected first and second decimal digit with said first digit being the lesser significant and said second digit being the more significant, said counter comprising: a. first and second binary down counter means connected in cascade, means for setting said first selected digit in said first counter means and means for setting said second digit in said second counter means; b. means for applying a pulsing input signal to said first counter means for causing said first and second counter means to count down from said set condition; c. a first group of leads connected to said first counter means and carrying a binary logic corresponding to the digit of said first counter means at any given time; d. a second group of leads connected to said second counter means and carrying a binary logic corresponding to the digit of said second counter means at any given time; e. first readout means having a first energizing lead, a decimal display unit, a first input for receiving a binary code and means for converting said binary code to a decimal number in said unit; f. second readout means having a second energizing lead, a decimal display unit, a second input for receiving a binary code and means for converting said binary code to a decimal number in said unit; g. a group of readout leads connected in parallel with said first and said second inputs of said first and second readout means; h. means for creating a succession of first and second signals; i. means responsive to creation of said first signal for connecting said first group of leads to said group of readout leads and for simultaneously energizing said first energizing lead; j. means responsive to creation of said second signal for connecting said second group of leads to said group of readout leads and for simultaneously energizing said second energizing lead; k. a first manually codable device for creating a first binary-coded logic corresponding to said first selected decimal digit, a second manually codable device for creating a second binary-coded logic corresponding to said second selected decimal digit, means for transferring said first coded logic into said first counter means and means for transferring said second coded logic into said second counter means; l. said first and second codable devices have an energizing input lead and each of said transferring means include a group of leads extending from said respective codable devices, a group of setting leads with said group of leads from both of said codable devices being connected to said setting leads, means for connecting said group of setting leads to said setting means of both of said first and said secoNd counter means and means responsive to creation of said first signal for energizing said energizing input lead of said first codable device and for simultaneously blocking said setting means of said second counter means, means responsive to creation of said second signal for energizing said energizing input lead of said second codable device and for simultaneously blocking said setting means of said first counter means whereby said first and second counter means are set to the first and second binary codes, respectively; and, m. counter blocking means for blocking both of said setting means of said first and said second counter means after said counter means are both set with said binary codes.

Claim 38

A digital counter as defined in claim 29 wherein said counter blocking means includes a circuit responsive to creation of said succession of first and second signals for blocking said setting means of said first and said second counter means after a set minimum time exceeding the time for creating at least one first and one second signal.

Claim 39

A digital counter as defined in claim 30 wherein said circuit includes means for blocking said pulse applying means for a time at least as long as said minimum time.

Claim 40

A digital counter for counting down from a selected first and second decimal digit with said first digit being the lesser significant and said second digit being the more significant, said counter comprising: a. first and second binary down counter means connected in cascade, means for setting said first selected digit in said first counter means and means for setting said second digit in said second counter means; b. means for applying a pulsing input signal to said first counter means for causing said first and second counter means to count down from said set condition; c. a first group of leads connected to said first counter means and carrying a binary logic corresponding to the digit of said first counter means at any given time; d. a second group of leads connected to said second counter means and carrying a binary logic corresponding to the digit of said second counter means at any given time; e. first readout means having a first energizing lead, a decimal display unit, a first input for receiving a binary code and means for converting said binary code to a decimal number in said unit; f. second readout means having a second energizing lead, a decimal display unit, a second input for reciving a binary code and means for converting said binary code to a decimal number in said unit; g. a group of readout leads connected in parallel with said first and said second inputs of said first and second readout means; h. means for creating a succession of first and second signals; i. means responsive to creation of said first signal for connecting said first group of leads to said group of readout leads and for simultaneously energizing said first energizing lead; j. means responsive to creation of said second signal for connecting said second group of leads to said group of readout leads and for simultaneously energizing said second energizing lead; and, k. first means for creating a first binary logic corresponding to the first decimal digit, second means for creating a second binary logic corresponding to the second decimal digit, a group of setting leads connected in parallel to the setting means of both first and second counter means, means responsive to creation of said first signal for applying said first binary logic to said group of setting leads and for simultaneously blocking said setting means of said second counter means, means re-sponsive to creation of said second signal for applying said second binary logic to said group of setting leads and for simultaneously blocking said setting means of said first counter means and means for blocking the setting means of both said first and second counter means after said first and second binary logic has been set therein.

Claim 41

A digital counter for counting down from a selected first and second decimal digit with said first digit being the lesser significant and said second digit being the more significant, said counter comprising: a. first and second binary down counter means connected in cascade, means for setting said first selected digit in said first counter means and means for setting said second digit in said second counter means; b. means for applying a pulsing input signal to said first counter means for causing said first and second counter means to count down from said set condition; c. a first group of leads connected to said first counter means and carrying a binary logic corresponding to the digit of said first counter means at any given time; d. a second group of leads connected to said second counter means and carrying a binary logic corresponding to the digit of said second counter means at any given time; e. first readout means having a first energizing lead, a decimal display unit, a first input for receiving a binary code and means for converting said binary code to a decimal number in said unit; f. second readout means having a second energizing lead, a decimal display unit, a second input for reciving a binary code and means for converting said binary code to a decimal number in said unit; g. a group of readout leads connected in parallel with said first and said second inputs of said first and second readout means; h. means for creating a succession of first and second signals; i. means responsive to creation of said first signal for connecting said first group of leads to said group of readout leads and for simultaneously energizing said first energizing lead; j. means responsive to creation of said second signal for connecting said second group of leads to said group of readout leads and for simultaneously energizing said second energizing lead; and, k. first means for creating a first binary logic corresponding to the first decimal digit, second means for creating a second binary logic corresponding to the second decimal digit, a group of setting leads connected in parallel to the setting means of both first and second counter means, means responsive to creation of said first signal for applying said first binary logic to said group of setting leads and for simultaneously blocking said setting means of said second counter means, means re-sponsive to creation of said second signal for applying said second binary logic to said group of setting leads and for simultaneously blocking said setting means of said first counter means and means for blocking the setting means of both said first and second counter means after said first and second binary logic has been set therein.

Claim 42

A digital counter as defined in claim 32 including means for blocking said pulse applying means until said binary logics hae been set into said first and second counter means.

Claim 43

A MOSFET integrated circuit adapted to be used in a digital counter having an external unit for creating first, second, third and fourth binary codes and for setting said codes into four binary counters located within said integrated circuit, said integrated circuit comprising: a. first, second, third and fourth four stage binary counter means connected in cascade and each adapted to be set with a binary coded decimal digit; b. four terminal means for receiving said first, second, third and fourth codes; c. means for connecting said terminal means to the respective stages of each of said counter means; d. separately controllable switching means between said connecting means and each of said binary counter means; e. means for creating a succession of first, second, third and fourth multiplexing signals; f. means responsive to creation of one of said signals for casuing said external unit to direct said first code to said terminal means; g. means responsive to creation of said one signal for actuating said logic switching means associated with a selected one of said binary counters; and, h. a first group of four leads connected to the respective stages of said first binary counter means for providing a readout code for said first counter means; i. a second group of four leads connected to the respective stages of said second binary counter means for providing a readout code for said second counter means; j. a third group of four leads connected to the respective stages of said third binary counter means for providing a readout code for said third counter means; k. a fourth group of four leads connected to the respective stages of said fourth binary counter means for providing a readout code for said fourth counter means; l. a logic switching means connected to each lead of said groups of leads and having outputs; m. a first logic gate having inputs connected to the switching means of the first stage lead of each of said first, second, third and fourth groups of leads; n. a second logic gate having inputs connected to the switching means of the second stage lead of each of said first, second, third and fourth groups of leads; o. a third logic gate having inputs connected to the switching means of the third stage lead of each of said first, second, third and fourth groups of leads; p. a fourth logic gate having inputs connected to the switching means of the fourth stage lead of each of said first, second, third and fourth groups of leads; q. four terminal means for feeding a readout code from said integrated circuit, said terminal means each being connected to one of said logic gates; and, r. means responsive to creation of said one signal for energizing said logic switching means associated with the four stages of said one binary counter means to pass the logic of said one binary counter to said four terminal means.

Claim 44

A MOSFET integrated circuit adapted to be used in a digital counter having an external unit for creating first, second, third and fourth binary codes and for setting said codes into four binary counters located within said integrated circuit, said integrated circuit comprising: a. first, second, third and fourth four stage binary counter means connected in cascade and each adapted to be set with a binary coded decimal digit; b. four terminal means for receiving said first, second, third and fourth codes; c. means for connecting said terminal means to the respective stages of each of said counter means; d. separately controllable switching means between said connecting means and each of said binary counter means; e. means for creating a succession of first, second, third and fourth multiplexing signals; f. means responsive to creation of one of said signals for casuing said external unit to direct said first code to said terminal means; g. means responsive to creation of said one signal for actuating said logic switching means associated with a selected one of said binary counters; and, h. a first group of four leads connected to the respective stages of said first binary counter means for providing a readout code for said first counter means; i. a second group of four leads connected to the respective stages of said second binary counter means for providing a readout code for said second counter means; j. a third group of four leads connected to the respective stages of said third binary counter means for providing a readout code for said third counter means; k. a fourth group of four leads connected to the respective stages of said fourth binary counter means for providing a readout code for said fourth counter means; l. a logic switching means connected to each lead of said groups of leads and having outputs; m. a first logic gate having inputs connected to the switching means of the first stage lead of each of said first, second, third and fourth groups of leads; n. a second logic gate having inputs connected to the switching means of the second stage lead of each of said first, second, third and fourth groups of leads; o. a third logic gate having inputs connected to the switching means of the third stage lead of each of said first, second, third and fourth groups of leads; p. a fourth logic gate having inputs connected to the switching means of the fourth stage lead of each of said first, second, third and fourth groups of leads; q. four terminal means for feeding a readout code from said integrated circuit, said terminal means each being connected to one of said logic gates; and, r. means responsive to creation of said one signal for energizing said logic switching means associated with the four stages of said one binary counter means to pass the logic of said one binary counter to said four terminal means.