US3787669A
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Test pattern generator
Assignee: International Business Machines Corp
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Filing: 1972-06-30
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Granted: 1974-01-22
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Expires: 1992-06-30
Abstract
Abstract A generic sequential digital pattern generator is disclosed for converting a serial data stream of n compacted pattern messages into a sequence of n parallel digital patterns. The generic invention comprises a decoding means connected to a serial data stream, for receiving a compacted pattern message and converting the message to a signal on one out of r decode lines, an output register having r binary storage cells connected to r output lines, and r modulo 2 adders in parallel. Each modulo 2 adder has an augend input and an addend input. Each augend input is connected to one decode line from the decoding means. Each addend input is connected to one input line from the register. When the decoding means receives a compacted pattern message, it executes a change in the binary state of a selected one of the r output lines. Two species of the invention are disclosed, a first digital pattern generator operating on a serial data stream of pattern messages compacted by a log2 r encoding scheme, and a second digital pattern generator operating on a serial data stream of pattern messages compacted by the Shannon-Fano encoding scheme.
Inventors
- 👤 E Muehldorf
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 18:40
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31919; G01R31/31921
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
131 words
A sequential digital pattern generator for converting a serial data stream of n compacted pattern messages into a sequence of n parallel digital patterns comprising: a decoding means connected to said serial data stream, for receiving a compacted pattern message and converting said message to a signal on one out of r decode lines, an output register having r binary storage cells connected to r output lines, r modulo 2 adders in parallel, each adder having an augend input an an addend input, each augend input being connected to one decoding line from said decoding means and each addend input being connected to one output line from said register, whereby each compacted pattern message executes a change in the binary state of a selected one out of said r output lines.
Claim 2
Dependent Claim
131 words
A sequential digital pattern generator for converting a serial data stream of n compacted pattern messages into a sequence of n parallel digital patterns comprising: a decoding means connected to said serial data stream, for receiving a compacted pattern message and converting said message to a signal on one out of r decode lines, an output register having r binary storage cells connected to r output lines, r modulo 2 adders in parallel, each adder having an augend input an an addend input, each augend input being connected to one decoding line from said decoding means and each addend input being connected to one output line from said register, whereby each compacted pattern message executes a change in the binary state of a selected one out of said r output lines.
Claim 3
Dependent Claim
89 words
The sequential digital pattern generator for converting a serial data stream of n compacted pattern messages into a sequence of n parallel digital patterns of claim 1, wherein said decoding means comprises: a second register for storing a number to the base m whose numerical value corresponds to the selected one out of r output lines to be changed, a base m to position decoder connected to said second register for converting said stored number to the base m to a signal on one out of r decode lines.
Claim 4
Dependent Claim
82 words
The sequential digital pattern generator for converting a serial data stream of n compacted pattern messages into a sequence of n parallel digital patterns of claim 1, wherein said decoding means comprises: a second register for storing a binary number whose numerical value corresponds to the selected one out of r output lines to be changed, a binary to position decoder connected to said second register for converting said stored binary number to a signal on one out of r decode line.
Claim 5
Dependent Claim
175 words
The sequential digital pattern generator for converting a serial data stream of n compacted pattern messages into a sequence of n parallel digital patterns of claim 1, wherein said decoding means comprises: a tree decoder having a plurality of nodal stages, each stage having a single gate at each of a plurality of nodes, with predetermined ones of said gates connected to predetermined ones of said modulo 2 adders, a counter connected to said tree decoder for counting the number of information bits arriving in the serial data stream and for sequentially connecting successive nodal stages in said tree decoder to said serial data stream, means connected to said counter and to said tree decoder for generating a reset signal after a selected one of said predetermined ones of said gates in said tree decoder, has decoded a predefined compacted pattern message and has caused a selected one out of said r modulo 2 adders to alter the binary state of a selected one out of the r binary storage cells in said output register.
Claim 6
Dependent Claim
129 words
A sequential test pattern generator, comprising: a first register for storing a first unit of binary data representing an initial test pattern, a second register for storing a second unit of data representing the location of a digit to be changed in said first unit of binary data. means to decide said second unit of data and change the selected binary digit in said first unit of data, so as to generate a next pattern in said first register, means for signaling said decode means when said second unit of data has been received in said second register, so that said decode means can execute the selected change in said first unit of binary data, whereby a sequential test pattern is generated having a single change per test cycle.
Claim 7
Dependent Claim
129 words
A sequential test pattern generator, comprising: a first register for storing a first unit of binary data representing an initial test pattern, a second register for storing a second unit of data representing the location of a digit to be changed in said first unit of binary data. means to decide said second unit of data and change the selected binary digit in said first unit of data, so as to generate a next pattern in said first register, means for signaling said decode means when said second unit of data has been received in said second register, so that said decode means can execute the selected change in said first unit of binary data, whereby a sequential test pattern is generated having a single change per test cycle.
Claim 8
Dependent Claim
203 words
A sequential test Pattern generator operating on an input data stream of test point address messages compacted by the Shannon-Fano data compaction code, comprising: a register for storing a first unit of binary data representing an initial test pattern, means connected to said register to change a selected binary digit in said first unit of binary data, so as to generate a next test pattern in said register, a tree decoder having a plurality of nodal stages, each stage having a signal gate at each of a plurality of nodes, with predetermined ones of said gates connected to said register changing means, a counter connected to said tree decoder for counting the number of bits arriving in the input data stream and for sequentially connecting successive nodal stages in said tree decoder to said input data stream, means connected to said counter and said tree decoder for generating a reset signal after a selected one of said predetermined ones of said gates in said tree decoder, has decoded a predefined test point address message and has caused said register change means to alter a selected bit in said register, whereby a sequential test pattern is generated having a single change per test cycle.
Claim 9
Dependent Claim
203 words
A sequential test Pattern generator operating on an input data stream of test point address messages compacted by the Shannon-Fano data compaction code, comprising: a register for storing a first unit of binary data representing an initial test pattern, means connected to said register to change a selected binary digit in said first unit of binary data, so as to generate a next test pattern in said register, a tree decoder having a plurality of nodal stages, each stage having a signal gate at each of a plurality of nodes, with predetermined ones of said gates connected to said register changing means, a counter connected to said tree decoder for counting the number of bits arriving in the input data stream and for sequentially connecting successive nodal stages in said tree decoder to said input data stream, means connected to said counter and said tree decoder for generating a reset signal after a selected one of said predetermined ones of said gates in said tree decoder, has decoded a predefined test point address message and has caused said register change means to alter a selected bit in said register, whereby a sequential test pattern is generated having a single change per test cycle.
Claim 10
Independent Claim
95 words
A method for converting a serial data stream of n compacted pattern messages into a sequence of n parallel digital patterns, comprising the steps of: decoding each compacted pattern message into one out of r decode signals, adding modulo 2 said decode signal to the binary digit stored in one out of r storage cells in an output storage register, substituting the sum from said addition step for the addend in said one out of r storage cells, whereby a new parallel digit pattern of r bits will be stored in the output storage register.
Claim 11
Independent Claim
95 words
A method for converting a serial data stream of n compacted pattern messages into a sequence of n parallel digital patterns, comprising the steps of: decoding each compacted pattern message into one out of r decode signals, adding modulo 2 said decode signal to the binary digit stored in one out of r storage cells in an output storage register, substituting the sum from said addition step for the addend in said one out of r storage cells, whereby a new parallel digit pattern of r bits will be stored in the output storage register.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-01-21 | 1977-07-23 | 1978-01-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-01-21 | 1981-07-23 | 1982-01-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-01-21 | 1985-07-23 | 1986-01-22 | $7700.00 | Window Closed / Lapsed |