Digital expandor circuit

Claim 2

A digital expandor circuit for effecting a nonlinear digital expansion of a compressed digital signal arranged in groups of pulses known as word groups, each word group having a first plurality of code digits called a characteristic and a second plurality of word digits called a mantissa comprising in combination: a shifting register having a plurality of stages equal to the number of digits in the expanded digital word; a counter circuit; means for reading a digit representing the most significant digit in said expanded word into said shift register; means for reading said mantissa into said shift register; means for reading said characteristic into said counter; means responsive to said counter circuit for conTrolling the shifting of said shift register so that said digit representing the most significant digit and said mantissa are positioned in the stages of said shift register corresponding to the positioning of the most significant bits in said expanded digital word; means responsive to said counter circuit for transferring digits from said shift register to the output of said expandor circuit; and means responsive to the least significant bit of the digits stored in said counter circuit for selectively inhibiting the transferral of said digit representing the most significant digit from said shift register to the output of said expandor circuit.

Claim 3

A digital expandor circuit for expanding an input binary word having a first group of bits which carry information as to the position of the most significant binary ''''1'''' in the expanded binary word and a second group of bits which carry information as to the character of the significant bits closest to the most significant binary ''''1'''' comprising in combination: a binary counter circuit; a shift register having a number of stages equal to the number of bits in the expanded binary word, each of the stages occupying positions which correspond to the position of the bits in the expanded binary word; means for reading said first group of bits in each of said input words into said counter circuit; means for reading said second group of bits in each of said input words in the stages of said shift register which correspond to the positions of the least significant bits in the expanded binary word; means for reading a binary ''''1'''' into said shift register in the stage corresponding to the position of the bit which is closest to and more significant than said least significant bits; means for providing a timing signal having a plurality of periodically occurring pulses for simultaneously activating said counter circuit and said shaft register, each of said pulses in said signal causing said counter circuit to count one binary unit in a predetermined counting cycle and said shift register to shift each of its bits to stages with positions which correspond to bits one step higher in significance; means responsive to said bits in said counter circuit for controlling said timing signal so that said shift register shifts its bits through a predetermined number of stages while said counter circuit counts a predetermined number of binary units; means for transferring the bits in said shift register to an output circuit; and means connected between said shift register and said output circuit for selectively inhibiting said most significant binary ''''1'''' when said bits in said counter circuit correspond to a predetermined binary code.

Claim 4

A digital expandor circuit for expanding an input binary word having a first group of bits which carry information as to the position of the most significant binary ''''1'''' in the expanded binary word and a second group of bits which carry information as to the character of the significant bits closest to the most significant binary ''''1'''' comprising in combination: a binary counter circuit; a shift register having a number of stages equal to the number of bits in the expanded binary word, each of the stages occupying positions which correspond to the position of the bits in the expanded binary word; means for reading said first group of bits in each of said input words into said counter circuit; means for reading said second group of bits in each of said input words in the stages of said shift register which correspond to the positions of the least significant bits in the expanded binary word; means for reading a binary ''''1'''' into said shift register in the stage corresponding to the position of the bit which is closest to and more significant than said least significant bits; means for providing a timing signal having a plurality of periodically occurring pulses for simultaneously activating said counter circuit and said shaft register, each of said pulses in said signal causing said counter circuit to count one binary unit in a predetermined counting cycle and said shift register to shift each of its bits to stages with positions which correspond to bits one step higher in significance; means responsive to said bits in said counter circuit for controlling said timing signal so that said shift register shifts its bits through a predetermined number of stages while said counter circuit counts a predetermined number of binary units; means for transferring the bits in said shift register to an output circuit; and means connected between said shift register and said output circuit for selectively inhibiting said most significant binary ''''1'''' when said bits in said counter circuit correspond to a predetermined binary code.

Claim 5

A digital expandor circuit for expanding an input binary word having a first group of bits which carry information as to the position of the most significant binary ''''1'''' in the expanded binary word and a second group of bits which carry information as to the character of the significant bits closest to the most significant binary ''''1'''' comprising in combination: a binary counter circuit; a shift register having a number of stages equal to the number of bits in the expanded binary word, each of the stages occupying positions which correspond to the positions of the bits in the expanded binary word; means for reading said first group of bits in each of said input words into said counter circuit; means for reading said second group of bits in each of said input words into the stages of said shift register which correspond to the positions of the least significant bits in the expanded binary word; means for reading a binary ''''1'''' into said shift register in the stage corresponding to the position of the bit which is closest to and more significant than said least significant bits; signal means for periodically activating said counter circuit and Said shift register, each of said periodic signals causing said counter circuit to count one unit in a predetermined counting cycle and said shift register to shift its bits as a group to stages with positions which correspond to bits one step higher in significance in the expanded binary word; means for controlling said signal means such that said shift register is activated only when said counter circuit is activated; means responsive to the character of the bits in said counter circuit for controlling the number of counts made by said counter circuit, said means permitting said counter to count in said predetermined counting cycle until the bits in said counter correspond to one of two predetermined binary codes; means for transferring the bits in said shift register to an output circuit; and means connected between said shift register and said output circuit for selectively inhibiting said most significant binary ''''1'''' when said bits in said counter circuit correspond to one of said predetermined binary codes.

Claim 6

A digital expandor circuit for expanding an input binary word having a first group of bits which carry information as to the position of the most significant binary ''''1'''' in the expanded binary word and a second group of bits which carry information as to the character of the significant bits closest to the most significant binary ''''1'''' comprising in combination: a binary counter circuit; a shift register having a number of stages equal to the number of bits in the expanded binary word, each of the stages occupying positions which correspond to the positions of the bits in the expanded binary word; means for reading said first group of bits in each of said input words into said counter circuit; means for reading said second group of bits in each of said input words into the stages of said shift register which correspond to the positions of the least significant bits in the expanded binary word; means for reading a binary ''''1'''' into said shift register in the stage corresponding to the position of the bit which is closest to and more significant than said least significant bits; signal means for periodically activating said counter circuit and Said shift register, each of said periodic signals causing said counter circuit to count one unit in a predetermined counting cycle and said shift register to shift its bits as a group to stages with positions which correspond to bits one step higher in significance in the expanded binary word; means for controlling said signal means such that said shift register is activated only when said counter circuit is activated; means responsive to the character of the bits in said counter circuit for controlling the number of counts made by said counter circuit, said means permitting said counter to count in said predetermined counting cycle until the bits in said counter correspond to one of two predetermined binary codes; means for transferring the bits in said shift register to an output circuit; and means connected between said shift register and said output circuit for selectively inhibiting said most significant binary ''''1'''' when said bits in said counter circuit correspond to one of said predetermined binary codes.