← Back to Patent Explorer
US3784907A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of propagation delay testing a functional logic system

Assignee: International Business Machines Corp
•
Filing: 1972-10-16
•
Granted: 1974-01-08
•
Expires: 1992-10-16
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract Propagation delay testing is performed on a generalized and modular logic system that is utilized as an arithmetic/logical unit in a digital computer. Each arithmetic/logical unit of a computer is formed of arrangements of combinational logic networks and storage circuitry. The storage circuitry has the capability for performing scan-in/scan-out operations independently of the system input/output and controls. Using this scan capability, the method of the invention provides for the state of the storage circuitry to be preconditioned and independent of its prior history. Selected propagation paths through the system circuitry are sensitized by test patterns from an automatic test generator. By altering selected inputs and cycling controls applied to the networks of combinational logic and their respective associated storage circuitry, propagation delay indications through the selected paths are obtained to determine the status of these path delays through the logic system.

Inventors

  • 👤 E Eichelberger

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-22 21:01
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037; G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31725; G01R31/3181; G01R31/3183; G01R31/318328; G01R31/3185; G01R31/318533; G01R31/318541; G01R31/318577; G01R31/31858; G01R31/318594; G06; G06F; G06F9/00; G06F9/06; G06F9/44; G06F9/448; G06F9/4482; G06F9/4484

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 135 words
A method of propagation delay testing a single-sided delay dependent functional logic unit having primary inputs and primary outputs and formed of combinational networks and sets of associated sequential circuits having access for scanning independent of said primary inputs and outputs, comprising the steps of selecting a predetermined path through at least a portion of said unit for test sensitization, initializing the states of said sets of circuits, applying a test pattern to at least Some of said primary inputs for said selected path, altering one of said primary inputs to the selected path, and measuring the output of said selected path for a change of state after a given period of time has elapsed from the altering of the primary input, whereby an indication of the propagation delay through the selected path is obtained.
Claim 2
Independent Claim 135 words
A method of propagation delay testing a single-sided delay dependent functional logic unit having primary inputs and primary outputs and formed of combinational networks and sets of associated sequential circuits having access for scanning independent of said primary inputs and outputs, comprising the steps of selecting a predetermined path through at least a portion of said unit for test sensitization, initializing the states of said sets of circuits, applying a test pattern to at least Some of said primary inputs for said selected path, altering one of said primary inputs to the selected path, and measuring the output of said selected path for a change of state after a given period of time has elapsed from the altering of the primary input, whereby an indication of the propagation delay through the selected path is obtained.
Claim 3
Dependent Claim 28 words
The method of claim 1, wherein initialization of the states of said set is accomplished by scanning a predetermined signal pattern into said sets through said scanning access.
Claim 4
Dependent Claim 29 words
The method of claim 2, wherein the method is repeated a plurality of times by selecting a plurality of paths and applying a plurality of test patterns in sequence.
Claim 5
Dependent Claim 33 words
The method of claim 2, wherein the output of the sensitized path is a primary output of the unit and the measuring is performed directly by observing any change in a primary output.
Claim 6
Dependent Claim 39 words
The method of claim 4, wherein the sensitized path commences at the primary inputs and passes through a combinational network and the direct measurement is made a given time after effecting an alteration in one of the primary inputs.
Claim 7
Dependent Claim 64 words
The method of claim 4, wherein some of said primary inputs are clock trains coupled respectively to the sets of sequential circuits and the sensitized path commences in a set of said sequential circuits and passes through a combinational network and the direct measurement is made a given time after effecting a change in the clock train for the set where the path commences.
Claim 8
Dependent Claim 80 words
The method of claim 3, wherein some of said primary inputs are clock trains coupled respectively to the sets of sequential circuits and the output of the sensitized path is in one of the sets of said sequential circuits and the measuring is performed by effecting a change in the clock train for the set having the output of said path and there-after scanning out the contents of said set for obtaining an indication of a change in said set.
Claim 9
Dependent Claim 48 words
The method of claim 7, wherein the sensitized path commences at the primary inputs and passes through a combinational network to said set of sequential circuits and the altering of the primary input occurs a predetermined period of time before a change is effected in the clock train.
Claim 10
Dependent Claim 63 words
The method of claim 7, wherein the sensitized path commences at one set of sequential circuits and passes through a combinational network to the output of said path in another set of said circuits and the altering of the primary input is accomplished by changing the clock train for the one set of circuits a predetermined period of time prior to the measuring.

References Cited (Backward Citations)

US3659088A Cited
US3714403A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-01-07 1977-07-09 1978-01-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-01-07 1981-07-09 1982-01-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-01-07 1985-07-09 1986-01-08 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag