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US3714403A
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Computer implemented method of detecting and isolating electrical faults in core memory systems
Assignee: AG Communication Systems Corp
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Filing: 1971-09-01
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Granted: 1973-01-30
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Expires: 1991-09-01
Abstract
Abstract A computer implemented method of detecting and isolating both permanent and intermittent electrical failures in core memory systems is based upon a unique code number associated with each potential failure and derived from the symmetry of the relationship among the memory components for any selected word. The address of each failing memory word is decoded and all of the decoded address fields are OR''ed, on a bit by bit basis to provide a code number indicative of a combination of word failures which is correlated to the specific component failure.
Inventors
- 👤 D Dorenbos
- 👤 R Ammann
- 👤 J Creasy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 22:57
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/56
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
102 words
A computer implemented method of detecting and isolating electrical faults in a core mEmory system comprising the steps of writing a preselected bit pattern into each word of said memory, reading each word in said memory, comparing each word read with said preselected pattern written into that word to thereby detect failing words through inequality of said word read with said word written, decoding the address of each said failing word, OR''ing the decoded addresses of all failing words in said memory to thereby generate a fault code number which is uniquely related to the electrical fault in said core memory system.
Claim 2
Dependent Claim
102 words
A computer implemented method of detecting and isolating electrical faults in a core mEmory system comprising the steps of writing a preselected bit pattern into each word of said memory, reading each word in said memory, comparing each word read with said preselected pattern written into that word to thereby detect failing words through inequality of said word read with said word written, decoding the address of each said failing word, OR''ing the decoded addresses of all failing words in said memory to thereby generate a fault code number which is uniquely related to the electrical fault in said core memory system.
Claim 3
Dependent Claim
102 words
A computer implemented method of detecting and isolating electrical faults in a core mEmory system comprising the steps of writing a preselected bit pattern into each word of said memory, reading each word in said memory, comparing each word read with said preselected pattern written into that word to thereby detect failing words through inequality of said word read with said word written, decoding the address of each said failing word, OR''ing the decoded addresses of all failing words in said memory to thereby generate a fault code number which is uniquely related to the electrical fault in said core memory system.
Claim 4
Dependent Claim
102 words
A computer implemented method of detecting and isolating electrical faults in a core mEmory system comprising the steps of writing a preselected bit pattern into each word of said memory, reading each word in said memory, comparing each word read with said preselected pattern written into that word to thereby detect failing words through inequality of said word read with said word written, decoding the address of each said failing word, OR''ing the decoded addresses of all failing words in said memory to thereby generate a fault code number which is uniquely related to the electrical fault in said core memory system.
Claim 5
Dependent Claim
20 words
The method recited in claim 1 wherein said preselected bit pattern is uniquely different for each word of said memory.
Claim 6
Dependent Claim
20 words
The method recited in claim 2 wherein said unique bit pattern is the address of each word of said memory.
Claim 7
Dependent Claim
19 words
The method recited in claim 1 wherein said preselected bit pattern is common to all words of said memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-01-30 | 1976-07-31 | 1977-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-01-30 | 1980-07-31 | 1981-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-01-30 | 1984-07-31 | 1985-01-30 | $7700.00 | Window Closed / Lapsed |