Abstract A program controlled computer which comprises independent control circuitry for exchanging data between registers of the computer and the computer memory independently of the execution of program. This arrangement saves computer time as it facilitates the storing and retrieving of data which must be saved during nesting and unnesting of program transfers. For each register that contains data which is to be saved upon the occurrence of a program interrupt, there is provided an auxiliary register and program controlled gates for exchanging data between the computer register and its corresponding auxiliary register. In the illustrative embodiment the computer is arranged to execute ''''save'''' and ''''restore'''' instructions which serve respectively to transfer the contents of a computer register to its auxiliary register and to transfer the contents of an auxiliary register to its associated computer register. The independent control circuitry monitors the busy and idle states of the computer memory and upon occurrence of periods of time in which the computer is not utilizing the computer memory, the independent control circuitry exchanges data between the auxiliary registers and the computer memory. Data is exchanged between the computer registers and their associated auxiliary registers simultaneously. However, data is exchanged between the auxiliary registers and the computer memory on a word-by-word serial basis.
In combination, memory means for storing information comprising sequences of program instructions and data, means for accessing said memory to read information from and to write information into said memory; a program controlled data processor for executing instructions of a set of instructions which set includes SAVE and RESTORE instructions comprising: instruction regIster means, instruction decoder means connected to said instruction register means for generating processor control signals corresponding to instructions stored in said instruction register means and including signals indicating the busy and idle states of said memory, a plurality of internal registers for storing data, means for controlling said memory accessing means to transfer instructions from said memory means to said instruction register means; a plurality of auxiliary registers corresponding in number and individually associated with certain of said internal registers, gating means responsive to certain of said processor control signals corresponding to said SAVE and RESTORE instructions for exchanging data between said certain registers and said individually associated auxiliary registers; and independent control means responsive to said certain processor control signals and to said memory idle signals for exchanging data between said auxiliary registers and said memory means.
Claim 2
Dependent Claim
191 words
In combination, memory means for storing information comprising sequences of program instructions and data, means for accessing said memory to read information from and to write information into said memory; a program controlled data processor for executing instructions of a set of instructions which set includes SAVE and RESTORE instructions comprising: instruction regIster means, instruction decoder means connected to said instruction register means for generating processor control signals corresponding to instructions stored in said instruction register means and including signals indicating the busy and idle states of said memory, a plurality of internal registers for storing data, means for controlling said memory accessing means to transfer instructions from said memory means to said instruction register means; a plurality of auxiliary registers corresponding in number and individually associated with certain of said internal registers, gating means responsive to certain of said processor control signals corresponding to said SAVE and RESTORE instructions for exchanging data between said certain registers and said individually associated auxiliary registers; and independent control means responsive to said certain processor control signals and to said memory idle signals for exchanging data between said auxiliary registers and said memory means.
Claim 3
Dependent Claim
95 words
The combination in accordance with claim 1 wherein said instruction decoder generates processor control signals to control said gating means to transfer the contents of said plurality of internal registers simultaneously to said individually associated auxiliary registers in response to the appearance of a SAVE instruction in said instruction register means and wherein said instruction decoder generates processor control signals to control said gating means to transfer the contents of said plurality of auxiliary registers simultanuously to said corresponding internal registers in response to the appearance of a RESTORE instruction in said instruction register means.
Claim 4
Dependent Claim
62 words
The combination in accordance with claim 1 wherein said independent control means is responsive to processor control signals indicating the appearance of a SAVE instruction in said instruction register and to said memory idle signals to store in said memory means the contents of said plurality of auxiliary registers on a serial word-by-word basis without altering the contents of said auxiliary registers.
Claim 5
Dependent Claim
122 words
The combination in accordance with claim 1 wherein said independent control means includes signal generating means to inhibit momentarily the execution of a program by said program controlled data processor upon the appearance of another SAVE instruction in said instruction register prior to the time said independent control means has completed transfer of the information content of said auxiliary registers to said memory in response to the appearance of an immediately preceding SAVE instruction in said instruction register and upon the appearance of another RESTORE instruction in said instruction register before said independent control means has completed transfer of data from said memory to said auxiliary registers in response to the appearance of an immediately preceding RESTORE instruction in said instruction register.