Apparatus and method for testing logic circuits and the like by the comparison of test output patterns with preprogrammed standard patterns

Claim 1

AN AUTOMATIC LOGIC TESTER FOR SEQUENTIALLY TESTING LOGIC CIRCUITS FOR FAULTY COMPONENTS, EACH OF THE LOGIC CIRCUITS HAVING AT LEAST ONE INPUT AND AN OUTPUT, SAID TESTER COMPRISING TEST RECORD MEANS FOR STORING TEST INFORMATION FOR PROGRAMMING A SERIES OF TESTS WHICH APPLY ALL MINIMIZED LOGICAL INPUT COMBINATIONS TO THE INPUTS OF SAID LOGIC CIRCUITS AND MAKE OTHER TESTS AS ARE NECESSARY TO DETERMINE THE IDENTITY OF FAULTY COMPONENTS, ANALAYSIS RECORD MEANS FOR STORING GO AND NO GO PATTERNS OF ANALYSIS TEST RESULTS WHICH WOULD OCCURFOR THE FAILURE OF DIFFERENT COMPONENTS IN THE TEST LOGIC CIRCUITS, MEANS FOR SELECTIVELY READING SAID TEST INFORMATION AND ANALYSIS RECORD MEANS, MEANS INCLUDING MEANS RESPONSIVE TO THE READ TEST INFORMATION FOR ENERGIZING THE LOGIC CIRCUITS SEQUENTIALLY AND FOR DETECTING A GO AND NO GO RESULT FOR EACH OF THE TESTS, A MEMORY INCLUDING AT LEAST ONE BI-STABLE STORAGE ELEMENT FOR STORING THE DETECTED TEST RESULTS IN A DEFINED SEQUENCE, TO PROVIDE A PATTERN OF THE DETECTED TEST RESULTS WHICH IS INDICATIVE OF THE FAILURE OF AT LEAST ONE OF THE COMPONENTS IN THE LOGIC CIRCUITS, MEANS FOR COMPARING THE GO AND NO GO PATTERNS OF ANALYSIS TEST RESULTS ON THE ANALYSIS RECORD MEANS WITH THE DETECTED TEST RESULTS IN SAID MEMORY AND PROVIDING A SIGNAL IN THE EVENT OF A COMPARE, AND MEANS ACTUATED BY THE COMPARE SIGNAL FOR PROVIDING A VISUAL INDICATION OF THE FAULTY COMPONENTS.