Current driver system for a core memory

Claim 1

A system for supplying a predetermined magnitude of current to a core memory, said system having minimal current buildup time inverval and minimal power supply drain, comprising: a transformer having a primary and a secondary winding; a first switch connected in series between said core memory and said power supply; a second switch connected in series with said power supply and said primary winding of said transformer; means connecting said transformer to said core stack so that the total current driven through said core stack when said primary winding is energized is greater than the current flow in said primary winding; control means coupled to said first and second switches for i. closing said first switch for a sufficient interval to drive a current of predetermined value through said core memory, and ii. opening said first switch after said second switch has been closed.

Claim 2

A system for supplying a predetermined magnitude of current to a core memory, said system having minimal current buildup time inverval and minimal power supply drain, comprising: a transformer having a primary and a secondary winding; a first switch connected in series between said core memory and said power supply; a second switch connected in series with said power supply and said primary winding of said transformer; means connecting said transformer to said core stack so that the total current driven through said core stack when said primary winding is energized is greater than the current flow in said primary winding; control means coupled to said first and second switches for i. closing said first switch for a sufficient interval to drive a current of predetermined value through said core memory, and ii. opening said first switch after said second switch has been closed.

Claim 11

A system for supplying a current pulse to a core memory, said system having a minimal current buildup time interval and a minimal power supply drain, comprising: means for initially energizing the core stack from said power supply through a current path having a minimal L/R time constant so that a current of predetermined value is driven through said core stack within a very short time interval; and means for maintaining said magnitude of current flowing through said core stack while reducing the power drain from said power supply, said means comprising a transformer coupled to said core stack and having a primary/secondary turns ratio such that current flowing through said core stack is greater in magnitude than the current drawn from said power supply.

Claim 12

A system for supplying a current pulse to a core memory, said system having a minimal current buildup time interval and a minimal power supply drain, comprising: means for initially energizing the core stack from said power supply through a current path having a minimal L/R time constant so that a current of predetermined value is driven through said core stack within a very short time interval; and means for maintaining said magnitude of current flowing through said core stack while reducing the power drain from said power supply, said means comprising a transformer coupled to said core stack and having a primary/secondary turns ratio such that current flowing through said core stack is greater in magnitude than the current drawn from said power supply.

Claim 13

A system drawing minimal power for supplying a current pulse of predetermined magnitude and minimal buildup time interval to the high inductance inhibit windings of a bit plane of a coincident current memory, comprising: a transformer having a primary and a secondary winding; means for connecting one end of said primary and secondary windings to a pair of inhibit windings of said bit plane, one of said windings being respectively threaded through a plurality of memory cores of said bit plane and the other of said windings being respectively threaded through the remaining memory cores of said bit plane; a power supply supplying a voltage of predetermined magnitude; a first transistor switch connected in series with said power supply and said pair of inhibit windings of said bit plane to provide a first current path through said inhibit windings when said first transistor switch is on; a second transistor switch connected in series with said power supply and said primary winding of said transformer to provide a second current path to said pair of inhibit windings of said bit plane when said second transistor is on and said first transistor switch is off; and time control means coupled to said first and second switches for i. turning said first transistor switch on for a sufficient time interval to drive a current of predetermined value through said pair of inhibit windings of said bit plane, and ii. turning off said first transistor switch after said second transistor switch has been turned on to decrease the current drawn from said power supply and thereby draw less power from said power supply while maintaining the desired magnitude of current through said pair of inhibit windings.

Claim 14

A system drawing minimal power for supplying a current pulse of predetermined magnitude and minimal buildup time interval to the high inductance inhibit windings of a bit plane of a coincident current memory, comprising: a transformer having a primary and a secondary winding; means for connecting one end of said primary and secondary windings to a pair of inhibit windings of said bit plane, one of said windings being respectively threaded through a plurality of memory cores of said bit plane and the other of said windings being respectively threaded through the remaining memory cores of said bit plane; a power supply supplying a voltage of predetermined magnitude; a first transistor switch connected in series with said power supply and said pair of inhibit windings of said bit plane to provide a first current path through said inhibit windings when said first transistor switch is on; a second transistor switch connected in series with said power supply and said primary winding of said transformer to provide a second current path to said pair of inhibit windings of said bit plane when said second transistor is on and said first transistor switch is off; and time control means coupled to said first and second switches for i. turning said first transistor switch on for a sufficient time interval to drive a current of predetermined value through said pair of inhibit windings of said bit plane, and ii. turning off said first transistor switch after said second transistor switch has been turned on to decrease the current drawn from said power supply and thereby draw less power from said power supply while maintaining the desired magnitude of current through said pair of inhibit windings.

Claim 17

The method for generating a current pulse of predetermined magnitude for driving a high inductance winding of a memory core stack comprising the steps of: energizing said core stack through a current path of minimum resistance and inductance so that a current of predetermined value flows through the core stack within a very short time interval; and subsequently energizing a transformer connected to said core stack so that the power drain is reduced while maintaining a desired magnitude of current flow through said core stack.

Claim 18

The method for generating a current pulse of predetermined magnitude for driving a high inductance winding of a memory core stack comprising the steps of: energizing said core stack through a current path of minimum resistance and inductance so that a current of predetermined value flows through the core stack within a very short time interval; and subsequently energizing a transformer connected to said core stack so that the power drain is reduced while maintaining a desired magnitude of current flow through said core stack.

Claim 19

The method for generating a current pulse of predetermined magnitude for driving a high inductance winding of a memory core stack comprising the steps of: energizing said core stack through a current path of minimum resistance and inductance so that a current of predetermined value flows through the core stack within a very short time interval; and subsequently energizing the primary winding of a transformer so that a current is caused to flow in the secondary winding such that the current flowing in said core stack is the sum of the currents flowing through said primary and secondary windings of said transformer.

Claim 20

The method for generating a current pulse of predetermined magnitude for driving a high inductance winding of a memory core stack comprising the steps of: energizing said core stack through a current path of minimum resistance and inductance so that a current of predetermined value flows through the core stack within a very short time interval; and subsequently energizing the primary winding of a transformer so that a current is caused to flow in the secondary winding such that the current flowing in said core stack is the sum of the currents flowing through said primary and secondary windings of said transformer.