US3576570A
Expired / Lapsed
US
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Synchronous timing scheme for a data processing system
Assignee: Unisys Corp
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Filing: 1968-12-12
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Granted: 1971-04-27
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Expires: 1988-12-12
Abstract
Abstract A scheme for synchronizing the transfer of information signals between a Line Terminal and an associated Modem at a computer site of a data processing system. The scheme involves the addition of a logical circuit, termed the Synchronous Timing Assembly, to an already existing Line Terminal. The added Synchronous Timing Assembly resynchronizes the Line Terminal generated receive clock signal each time two incoming information signals, such as a Mark signal and a Space signal that are received sequentially from the Modem, differ in state. Additionally, the Synchronous Timing Assembly enables the Line Terminal to discriminate between valid and invalid information signals by dropping out all information signals not meeting established criteria.
Inventors
- 👤 Howard L Meier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:05
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0331; G; G06; G06F; G06F3/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
160 words
In an apparatus for synchronizing the transfer of binary information, the combination comprising: input signal means for receiving an input signal of first and second input signal levels and of 1-bit length in duration; delayed input signal means for transmitting a delayed input signal of first and second delayed input signal levels and of 1-bit length in duration; transmit clock signal generator means for generating a transmit clock signal; 1/2 -bit delay probe generator means; means coupling said transmit clock signal generator means to said 1/2 -bit delay probe generator means and means coupling said input signal means to said 1/2 -bit delay probe generator means for generating a 1/2 -bit delay probe signal; means coupling said 1/2 -bit delay probe signal and said input signal to said delayed input signal means for causing said delayed input signal means to generate a delayed input signal whose signal levels that correspond to corresponding input signal levels are delayed 1/2 -bit time.
Claim 2
Dependent Claim
160 words
In an apparatus for synchronizing the transfer of binary information, the combination comprising: input signal means for receiving an input signal of first and second input signal levels and of 1-bit length in duration; delayed input signal means for transmitting a delayed input signal of first and second delayed input signal levels and of 1-bit length in duration; transmit clock signal generator means for generating a transmit clock signal; 1/2 -bit delay probe generator means; means coupling said transmit clock signal generator means to said 1/2 -bit delay probe generator means and means coupling said input signal means to said 1/2 -bit delay probe generator means for generating a 1/2 -bit delay probe signal; means coupling said 1/2 -bit delay probe signal and said input signal to said delayed input signal means for causing said delayed input signal means to generate a delayed input signal whose signal levels that correspond to corresponding input signal levels are delayed 1/2 -bit time.
Claim 3
Dependent Claim
70 words
The combination of claim 1 further including: receive clock signal generator means for generating a receive clock signal; synchronizing signal means; means coupling said delayed input signal means to said synchronizing signal means for generating a synchronizing signal; means coupling said synchronizing signal to said receive clock signal generator means for clearing said receive clock signal generator means and for synchronizing said receive clock signal with said delayed input signal.
Claim 4
Dependent Claim
48 words
The combination of claim 2 further including an oscillator means for driving said transmit clock signal generator means and said receive clock signal generator means and generating transmit clock signals and receive clock signals of first and second clock signal levels each of 1/2 -bit length in duration.
Claim 5
Dependent Claim
62 words
The combination of claim 3 wherein said means coupling said 1/2 -bit delay probe signal and said input signal to said delayed input signal means includes a receive FF which changes state every time said 1/2 -bit delay probe signal and said input signal which produced the 1/2 -bit delay probe signal are coincident at the end of a 1/2 -bit time.
Claim 6
Dependent Claim
151 words
In an apparatus for synchronizing the transfer of binary information, the combination comprising: input signal means for receiving an input signal of first and second input signal levels; delayed input signal means coupled to said input signal means for transmitting a delayed input signal, of first and second delayed input signal levels, that is representative of said input signal; oscillator means including: transmit clock signal generator means for generating a tranSmit clock signal; and receive clock signal generator means for generating a receive clock signal; 1/2 -bit delay probe generator means driven by said transmit clock signal generator means for generating a 1/2 -bit delay probe signal; means coupling said 1/2 -bit delay probe signal and said input signal to said delayed input signal means for causing said delayed input signal means to transmit delayed input signal representations of said input signal that are at least 1/2 -bit length in duration.
Claim 7
Dependent Claim
151 words
In an apparatus for synchronizing the transfer of binary information, the combination comprising: input signal means for receiving an input signal of first and second input signal levels; delayed input signal means coupled to said input signal means for transmitting a delayed input signal, of first and second delayed input signal levels, that is representative of said input signal; oscillator means including: transmit clock signal generator means for generating a tranSmit clock signal; and receive clock signal generator means for generating a receive clock signal; 1/2 -bit delay probe generator means driven by said transmit clock signal generator means for generating a 1/2 -bit delay probe signal; means coupling said 1/2 -bit delay probe signal and said input signal to said delayed input signal means for causing said delayed input signal means to transmit delayed input signal representations of said input signal that are at least 1/2 -bit length in duration.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-04-26 | 1974-10-26 | 1975-04-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-04-26 | 1978-10-26 | 1979-04-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-04-26 | 1982-10-26 | 1983-04-27 | $7700.00 | Window Closed / Lapsed |