Schottky barrier type field effect transistor

Claim 2

A Schottky barrier gate field effect transistor comprising a substrate of high resistivity, an n-type gallium arsenide layer formed on said substrate; source and drain electrodes attached to said gallium arsenide layer, and a gate electrode formed on a portion of the surface of said gallium arsenide layer between said source and drain electrodes, said gate electrode being made of a metal selected from the group consisting of aluminum, gold, nickel and chromium, said gallium arsenide layer having an impurity concentration ranging from 1 X 1015cm 3 to 1 X 1016cm 3 and a thickness meeting the condition given by 2 X 103cm 1/2< W . square root N < 3 X 103cm 1/2 where N and W represent, respectively, said impurity concentration and the thickness of said gallium arsenide layer measured at the portion of said layer lying beneath said gate electrode, whereby said field effect transistor is enabled to function in the enhancement mode.

Claim 3

A Schottky barrier gate field effect transistor comprising a substrate of high resistivity, an n-type silicon layer formed on said substrate, source and drain electrodes attached to said silicon layer, and a gate electrode formed on a portion of the surface of said n-type silicon layer between said source and drain electrodes, said gate electrode being made of a material selected from the group consisting of molybdenum, platinum, gold, palladium, platinum silicide and palladium silicide, wherein said silicon layEr has an impurity concentration ranging from 1 X 1016cm 3 to 5 X 1016cm 3 and a thickness meeting the condition given by 2 X 103cm 1/2< W . Square Root N < 3 X 103cm 1/2 where N and W represent, respectively, said impurity concentration and the thickness of said silicon layer measured at the portion of said layer lying beneath said gate electrode, whereby said field effect transistor is enabled to function in the enhancement mode.

Claim 4

A Schottky barrier gate field effect transistor comprising a substrate of high resistivity, an n-type silicon layer formed on said substrate, source and drain electrodes attached to said silicon layer, and a gate electrode formed on a portion of the surface of said n-type silicon layer between said source and drain electrodes, said gate electrode being made of a material selected from the group consisting of molybdenum, platinum, gold, palladium, platinum silicide and palladium silicide, wherein said silicon layEr has an impurity concentration ranging from 1 X 1016cm 3 to 5 X 1016cm 3 and a thickness meeting the condition given by 2 X 103cm 1/2< W . Square Root N < 3 X 103cm 1/2 where N and W represent, respectively, said impurity concentration and the thickness of said silicon layer measured at the portion of said layer lying beneath said gate electrode, whereby said field effect transistor is enabled to function in the enhancement mode.

Claim 5

The transistor as claimed in claim 2, wherein said gate electrode is made of platinum silicide and wherein the thickness of the portion of said semiconductor layer lying beneath said gate electrode is in the range from 0.15 Mu to 0.3 Mu .