Multi-microprogrammed input-output processor

Claim 1

In combination with a CAMAC multiple channel data acquisition system including a plurality of crates each containing a plurality of data channel modules and a crate control means for controlling the operation of each of said plurality of data channel modules and the transfer of data into and out of said data channel modules, a microprogrammable input-output processor for multiplexing data channels of said multiple channel data acquisition system through a plurality of direct memory access channels to a host computer via a single direct memory access interface in which command lists stored in the computer memory select microprogrammed sequences which transfer data between the multiple channel data acquisition system and data lists in the computer memory, comprising: a source bus; a destination bus; a computer interface connected to said source bus and said destination bus for providing computer access to said buses; a control memory means having access to said source bus and said destination bus for storing data transfer microprograms in thE form of instruction sets for controlling the transfer of data between said multiple channel data acquisition system and said computer interface; an instruction register coupled to said control memory means for accepting instruction sets from said control memory means to be executed; a decode and control circuit connected to said instruction register for generating control signals at respective outputs in accordance with said instruction sets to execute transfers of data through said processor under control of a selected one of said microprograms; a multiple channel file register means corresponding in number to said plurality of direct memory access channels and accessible by said source bus and said destination bus for storing information from lists in said computer to control and address data transfers through said processor; a channel priority selection means for determining the highest priority channel of said multiple channel data acquisition system requesting service and selecting the corresponding channel of said multiple channel file register for initialization of a data block transfer between one of said channels of said multiple channel data acquisition system and said host computer; and means controlled by said decode and control circuit for performing programmed digital arithmetic and logical operations on data word transfers between said source bus and said destination bus and transferring the assigned computer address for said data word transfers from said multiple channel file register means into said host computer.