US3764790A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Technique for extending the frequency range of digital dividers
Assignee: National Aeronautics and Space Administration
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Filing: 1972-03-30
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Granted: 1973-10-09
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Expires: 1992-03-30
Abstract
Abstract A technique for extending the frequency range of a presettable digital divider. The conventional digital divider consists of several counter stages with the count of each stage compared to a preselected number. When the counts for all stages are equal to the preselected numbers, an output pulse is generated and all stages are reset. For high input frequencies, the least significant stage of the divider has to be reset in a very short time. This limits the frequency that can be handled by the conventional digital divider. This invention provides a technique in which the second least significant and higher stages are reset and the least significant stage is permitted to free-run. Hence, the time in which the reset operation can be performed is increased thereby extending the frequency range of the divider.
Inventors
- 👤 W Long
- 👤 J Middleton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 18:58
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/64; H03K23/66; H03K23/665; H03K23/667
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
257 words
A digital divider for producing output pulses having a frequency F/N where F is the frequency of the input pulses to the divider and N is a preselected multidigit number with the least significant digit Z of N being to the base B, comprising: means for producing signals representing each of the digits of said number N; first counter means having B states, receiving said input pulses and in response thereto continuously recycling through its B states, for producing signals indicative of its states at all times; control circuit means receiving the signals representing Z and the signals indicative of the states of said first counter means for producing a pulse each time B-1 input pulses are received by said first counter means until B-Z pulses are produced and thereafter producing a pulse each time B input pulses are received by said first counter means until a reset pulse is received by the control circuit means; second counter means for counting the pulses produced by said control circuit means and for producing signals indicative of the count minus one; comparator means for comparing the signals produced by said second counter means with said signals representing each of the digits of said number N except Z and for producing an output pulse whenever the signals are equal; and means for applying each of said output pulses to said control circuit means and said second counter means to reset them whereby said output pulses have a frequency F/N and a time of B/F is allowable for said reset operation.
Claim 2
Dependent Claim
257 words
A digital divider for producing output pulses having a frequency F/N where F is the frequency of the input pulses to the divider and N is a preselected multidigit number with the least significant digit Z of N being to the base B, comprising: means for producing signals representing each of the digits of said number N; first counter means having B states, receiving said input pulses and in response thereto continuously recycling through its B states, for producing signals indicative of its states at all times; control circuit means receiving the signals representing Z and the signals indicative of the states of said first counter means for producing a pulse each time B-1 input pulses are received by said first counter means until B-Z pulses are produced and thereafter producing a pulse each time B input pulses are received by said first counter means until a reset pulse is received by the control circuit means; second counter means for counting the pulses produced by said control circuit means and for producing signals indicative of the count minus one; comparator means for comparing the signals produced by said second counter means with said signals representing each of the digits of said number N except Z and for producing an output pulse whenever the signals are equal; and means for applying each of said output pulses to said control circuit means and said second counter means to reset them whereby said output pulses have a frequency F/N and a time of B/F is allowable for said reset operation.
Claim 3
Dependent Claim
200 words
A digital divider according to claim 1 wherein said control circuit means comprises: third counter means having B states which counts down one each time a pulse is applied to it including means for producing signals indicative of the count on the counter; fourth counter means having B states which counts down one each time a pulse is applied to it and which resets to zero each time one of said output pulses is applied to it including means for producing signals indicative of the count on the counter; an AND gate having its output connected to said third and fourth counters; second comparator means for comparing said signals representing Z and said signals representing the count on said fourth counter means for applying an enabling signal to said AND gate while said signals are different and for applying an inhibit signal to said AND gate while said signals are equal; and third comparator means for comparing said Signals indicative of the states of said first counter means with said signals indicative of the count on said third counter means for applying a pulse each time the signals are equal to said second counter means and to said AND gate.
Claim 4
Dependent Claim
147 words
In a digital divider for producing output pulses having a frequency F/N where F is the frequency of the input pulses to the divider and N is a preselected multi-digit number with the least significant digit Z of N being to the base B; means for producing signals representing Z; first counter means having B states, receiving said input pulses and in response thereto continuously recycling through its B states for producing signals indicative of its states at all times; and control circuit means receiving the signals representing Z and the signals indicative of the states of said counter means for producing a pulse each time B-1 input pulses are received by said counter means until B-Z pulses are produced and thereafter producing a pulse each time B input pulses are received by said counter means until a reset pulse is received by the control circuit means.
Claim 5
Dependent Claim
147 words
In a digital divider for producing output pulses having a frequency F/N where F is the frequency of the input pulses to the divider and N is a preselected multi-digit number with the least significant digit Z of N being to the base B; means for producing signals representing Z; first counter means having B states, receiving said input pulses and in response thereto continuously recycling through its B states for producing signals indicative of its states at all times; and control circuit means receiving the signals representing Z and the signals indicative of the states of said counter means for producing a pulse each time B-1 input pulses are received by said counter means until B-Z pulses are produced and thereafter producing a pulse each time B input pulses are received by said counter means until a reset pulse is received by the control circuit means.
Claim 6
Dependent Claim
193 words
In a digital divider according to claim 3 wherein said control circuit means comprises: second counter means having B states which counts down one each time a pulse is applied to it including means for producing signals indicative of the count on the counter; third counter means having B states which counts down one each time a pulse is applied to it and which resets to zero each time a reset pulse is applied to it including means for producing signals indicative of the count on the counter; an AND gate having its output connected to said second and third counters; first comparator means for comparing said signals representing Z and said signals representing the count on said third counter means for applying an enabling signal to said AND gate while said signals are different and for applying an inhibit signal to said AND gate while said signals are equal; and second comparator means for comparing said signals indicative of the states of said first counter means with said signals indicative of the count on said second counter means for applying a pulse each time the signals are equal to said AND gate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-10-08 | 1977-04-09 | 1977-10-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-10-08 | 1981-04-09 | 1981-10-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-10-08 | 1985-04-09 | 1985-10-09 | $7700.00 | Window Closed / Lapsed |