Digital and analog data handling devices

Claim 2

The combination in a charge transfer circuit of: a plurality of charge transfer stages connected in series for forming a serial shift register; first clock means coupled to said serial shift register for transferring charge signals in series along said serial shift register; a plurality of parallel registers, each one of said parallel registers comprising a multiplicity of charge transfer stages connected in series; means connecting each one of said parallel register to a different one of the stages of said serial shift register; and second clock means coupled to said parallel registers for transferring charge signals, in parallel, between said serial register and said parallel registers and for simultaneously shifting the charges stored in said parallel registers from stage to stage.

Claim 3

The combination as set forth in claim 1, wherein said stages of said registers comprise stages of the bucket brigade type.

Claim 4

The combination as claimed in claim 1: wherein said serial shift register is an output register having a plurality of input nodes and an output terminal; and wherein each one of said plurality of parallel registers is connected to a different one of said input nodes.

Claim 5

The combination in a charge transfer circuit of: a plurality of charge transfer registers, each register comprising a plurality of charge transfer stages connected in series; means for supplying charge signals to all of said registers; and means for reading out said charge signals including; a) an output register, comprised of a plurality of charge transfer stages, coupled to the last one of the stages of each of said plurality of registers; and b) shift means coupled to said output register for shifting from stage to stage along said output register the charge signals from said last stage of said plurality of registers; and means for shifting the charge signals stored in said plurality of registers, in parallel, from each stage to the next adjacent stage each time said output register is emptied.

Claim 6

The combination in a charge transfer circuit of: a plurality of charge transfer registers, each register comprising a plurality of charge transfer stages connected in series; means for supplying charge signals to all of said registers; and means for reading out said charge signals including; a) an output register, comprised of a plurality of charge transfer stages, coupled to the last one of the stages of each of said plurality of registers; and b) shift means coupled to said output register for shifting from stage to stage along said output register the charge signals from said last stage of said plurality of registers; and means for shifting the charge signals stored in said plurality of registers, in parallel, from each stage to the next adjacent stage each time said output register is emptied.

Claim 7

The combination comprising: a matrix array of elements, said aRray having N rows and M columns with an element being coupled between a row and a column at the intersection of said rows and columns; an output register having at least M input nodes and an output terminal, each node adapted to receive an input signal, said register for serially propagating the signals applied at its input nodes to said output terminal; charge transfer means coupled between each one of said M columns and one of said M input nodes for transferring in parallel the signals from said columns to said input nodes during one time interval; and means for applying clock signals to said output register for transferring the signals serially along said output register during a second time interval.

Claim 8

The combination comprising: a matrix array of elements, said aRray having N rows and M columns with an element being coupled between a row and a column at the intersection of said rows and columns; an output register having at least M input nodes and an output terminal, each node adapted to receive an input signal, said register for serially propagating the signals applied at its input nodes to said output terminal; charge transfer means coupled between each one of said M columns and one of said M input nodes for transferring in parallel the signals from said columns to said input nodes during one time interval; and means for applying clock signals to said output register for transferring the signals serially along said output register during a second time interval.

Claim 9

The combination as claimed in claim 5 wherein said charge transfer means includes two transistors per column, said two transistors having their source-drain paths connected between a column and an input point; and wherein said charge transfer means includes means for applying a transfer pulse to one of said two transistors for transferring the column signal to the drain of said one transistor and means for coupling a gating pulse to the other one of said two transistors for transferring the signal from the drain of said one transistor to said input point.

Claim 10

The combination as claimed in claim 6 wherein said matrix array is an image sensor and wherein said elements are photoresponsive elements.

Claim 11

The combination as claimed in claim 6 wherein said output register is of the bucket brigade type.

Claim 12

The combination as claimed in claim 6 wherein said matrix array is a memory array and wherein said elements are memory storage elements for storing bits of information.

Claim 13

The combination as claimed in claim 6 further including an input register having an input terminal and at least M output nodes; charge transfer means coupled between each one of said M output nodes and one of said columns; and clock means coupled to said charge transfer means for selectively transferring signals from said M output nodes onto said M columns.

Claim 14

The combination comprising: a matrix array of photoresponsive elements having N rows and M columns, a photoresponsive element being coupled between a row and a column at each intersection of said rows and columns; a vertical scan generator having at least N outputs each connected to one of said N rows for energizing said rows; an output register having at least M input nodes and an output terminal; said output register for serially propagating the signals applied to its input nodes for producing a serial output at said output terminal; charge transfer means for coupling each one of said columns to a different one of said input node, each column being coupled to an input node by means of two transistors having their source-drain paths connected in series between a column and an input node; means for selectively energizing said charge transfer means for transferring in parallel photo signals from said columns to their corresponding input nodes; and means for clocking said output register for advancing the signals serially.

Claim 15

The combination comprising: a matrix array of photoresponsive elements having N rows and M columns, a photoresponsive element being coupled between a row and a column at each intersection of said rows and columns; a vertical scan generator having at least N outputs each connected to one of said N rows for energizing said rows; an output register having at least M input nodes and an output terminal; said output register for serially propagating the signals applied to its input nodes for producing a serial output at said output terminal; charge transfer means for coupling each one of said columns to a different one of said input node, each column being coupled to an input node by means of two transistors having their source-drain paths connected in series between a column and an input node; means for selectively energizing said charge transfer means for transferring in parallel photo signals from said columns to their corresponding input nodes; and means for clocking said output register for advancing the signals serially.

Claim 16

The combination comprising: a plurality of transistors, each transistor having first and second regions defining the ends of a conduction path, a control electrode and a charge storage means coupled between the control electrode and the second region; N of said transistors having their conduction paths connected in series for forming a series transmission path, the second region of every other one of said N transistors forming an input-output point; M parallel paths, each connected at one end to a different one of said input-output points, each path comprising W of said plurality of transistors having their conduction paths connected in series; first means connected to the control electrode of every other one of said N transistors and second means connected to the control electrode of the remaining ones of said N transistors for alternately enabling every other one of said N transistors and then the remaining ones of said N transistors for sequentially transferring charge signals from one charge storage means to the next along said series path; and third means connected to the control electrode of every other one of said W transistors and fourth means connected to the control electrode of the remaining ones of said W transistors for alternately enabling every other one of said W transistors for transferring charge signals between said input-output points of said series path and said M paths and for concurrently sequentially transferring charge signals from one charge storage means to the next along said M paths; where M, N, and W are integers.

Claim 17

The combination comprising: a plurality of transistors, each transistor having first and second regions defining the ends of a conduction path, a control electrode and a charge storage means coupled between the control electrode and the second region; N of said transistors having their conduction paths connected in series for forming a series transmission path, the second region of every other one of said N transistors forming an input-output point; M parallel paths, each connected at one end to a different one of said input-output points, each path comprising W of said plurality of transistors having their conduction paths connected in series; first means connected to the control electrode of every other one of said N transistors and second means connected to the control electrode of the remaining ones of said N transistors for alternately enabling every other one of said N transistors and then the remaining ones of said N transistors for sequentially transferring charge signals from one charge storage means to the next along said series path; and third means connected to the control electrode of every other one of said W transistors and fourth means connected to the control electrode of the remaining ones of said W transistors for alternately enabling every other one of said W transistors for transferring charge signals between said input-output points of said series path and said M paths and for concurrently sequentially transferring charge signals from one charge storage means to the next along said M paths; where M, N, and W are integers.

Claim 18

The combination as claimed in claim 12 wherein said series register is an output register having its last input-output point connected to a signal output terminal wherein said first means includes means for applying a first clock signal to said control electrode of every other one of said N transistors; wherein said third means includes means for applying second clock signals to said control electrode of every other one of said W transistors; wherein said second and fourth means includes means for applying a reference potential to said control electrodes of said remaining transistors; and wherein said first and second clock signals vary in amplitude about said reference potential.

Claim 19

The combination as claimed in claim 12 further including a matrix of Z row conductors, where Z is an integer, and a multiplicity of column conductors, the intersection of each row and column conductor defining a bit location, each bit location including a gating transistor and a storage element; said gating transistor being connected at its control electrode to a row conductor, at one end of its conduction path to a column conductor and at the other end of its conduction path to said charge storage element; and means coupling each one of said column conductors to a different one of said M parallel paths.

Claim 20

The combination as claimed in claim 14 wherein said charge storage element is the junction capacitance of a diode, said diode having one of its anode and cathode connected to said gating transistor and having the other one of said anode and cathode connected to a point of fixed potential having a magnitude to maintain said diode reverse biased.

Claim 21

The combination comprising: first and second signal translating paths, each path comprising a plurality of charge transfer stages, said first path having an input terminal for the application thereto of input signals and at least one output node per stage and said second path having at least one input node per stage and an output terminal for producing thereat output signals in response to said input signals but delayed in time therefrom; N additional signal translating paths, each path connected between a different one of the output nodes of said first path and a different one of the input nodes of said second path; each one of said N additional paths comprising a plurality of charge transfer stages; means for applying clocking signals having a first rate to said first and second paths for serially propagating signals along said paths at said first rate; means for selectively applying clocking pulses having a second rate to said N paths for transferring data from said first path onto said N paths and from said N paths onto said second path; and each of said paths comprising transistors having first and second regions defining the ends of a conduction path, a control electrode, and exhibiting capacitance between the control electrode and the second region of each transistor; said transistors having their conduction paths direct current connected in series, every two transistors of said first and second paths forming one charge transfer stage and the second region of every other traNsistor being an input or an output node.

Claim 22

The combination comprising: first and second signal translating paths, each path comprising a plurality of charge transfer stages, said first path having an input terminal for the application thereto of input signals and at least one output node per stage and said second path having at least one input node per stage and an output terminal for producing thereat output signals in response to said input signals but delayed in time therefrom; N additional signal translating paths, each path connected between a different one of the output nodes of said first path and a different one of the input nodes of said second path; each one of said N additional paths comprising a plurality of charge transfer stages; means for applying clocking signals having a first rate to said first and second paths for serially propagating signals along said paths at said first rate; means for selectively applying clocking pulses having a second rate to said N paths for transferring data from said first path onto said N paths and from said N paths onto said second path; and each of said paths comprising transistors having first and second regions defining the ends of a conduction path, a control electrode, and exhibiting capacitance between the control electrode and the second region of each transistor; said transistors having their conduction paths direct current connected in series, every two transistors of said first and second paths forming one charge transfer stage and the second region of every other traNsistor being an input or an output node.

Claim 23

A memory system comprising: input and output signal registers, each register comprising a plurality of charge transfer stages, said input register having an input terminal for the application thereto of input signals and at least one output node per stage, and said output register having at least one input node per stage and an output terminal for producing output signals; a plurality of charge storage elements; a matrix of M row conductors and N column conductors, the intersection of each row and column conductor defining a bit location, each bit location including a transistor having its control electrode connected to a row conductor, one end of its conduction path connected to a column conductor and the other end of its conduction path connected to a charge storage element; means for selectively enabling said row and column conductors for transferring charge from said columns to said charge storage elements during a write-in period, and for transferring the charge sotred in said storage elements back to said column conductors during a read-out period; N charge transfer circuit means each connected between a different one of said output nodes of said input register and said N columns for transferring, when enabled, the information from said output nodes to said column conductors; and N other charge transfer circuit means each connected between a different one of said column conductors and a different one of said input nodes of said output register for, transferring, when enabled, the information from said column conductors to said output register.

Claim 24

A memory system comprising: input and output signal registers, each register comprising a plurality of charge transfer stages, said input register having an input terminal for the application thereto of input signals and at least one output node per stage, and said output register having at least one input node per stage and an output terminal for producing output signals; a plurality of charge storage elements; a matrix of M row conductors and N column conductors, the intersection of each row and column conductor defining a bit location, each bit location including a transistor having its control electrode connected to a row conductor, one end of its conduction path connected to a column conductor and the other end of its conduction path connected to a charge storage element; means for selectively enabling said row and column conductors for transferring charge from said columns to said charge storage elements during a write-in period, and for transferring the charge sotred in said storage elements back to said column conductors during a read-out period; N charge transfer circuit means each connected between a different one of said output nodes of said input register and said N columns for transferring, when enabled, the information from said output nodes to said column conductors; and N other charge transfer circuit means each connected between a different one of said column conductors and a different one of said input nodes of said output register for, transferring, when enabled, the information from said column conductors to said output register.

Claim 25

The combination as claimed in claim 17 further including capacitance means connected between each column and a common point, and including means for applying pulses to said common point for selectively pulsing the column conductors.

Claim 26

The combination as claimed in claim 18 wherein each one of said N means connected between the input register and the N columns includes the conduction path of an input gating transistor connected between each column and a different one of said output nodes of said input register, and wherein the control electrodes of said input gating transistors are connected in common to an input gate line for the application thereto of control signals for selectively transferring information from said output nodes of said input register to their associated columns.

Claim 27

The combination as claimed in claim 18 wherein each one of said N means connected between said columns and said output register includes: a) two transistors having their conduction paths connected in series between a column and an input point of said output register; b) means for applying a relatively long store pulse to the control electrode of that one of the two transistors connected to the column for transferring charge from the column capacitor and the drain node of said one of the two transistors; and c) means for applying a relatively short gating pulse to the control electrode of the other one of said two transistors.

Claim 28

The combination as claimed in claim 3: further including a plurality of charge transfer stages connected in series for forming a serial input register; said input register having a plurality of output nodes and an input terminal; means coupling each one of said output nodes to a different one of said parallel register; clock means having the same rate as said first clock means coupled to said input register; wherein said first clock means produces clock signals having a frequency f1; and wherein said second clock means produces clock signals having a frequency f2 wherein f2 is approximately equal to f1 divided by the number of stages in said serial shift register.

Claim 29

The combination as claimed in claim 16: wherein said second rate is approximately equal to said first rate divided by the number of transfer stages in said first path.