Memory control system adaptive to different access and cycle times

Claim 2

Timing and control logic for coupling a data processor and any memory of a plurality of memories having different memory access times and different memory cycle times, said logic comprising: A. means for providing a memory cycle initiate request indicating that said processor has provided an address for addressing said memory; B. means, responsive to said request, for generating a data ready signal indicating that the location addressed in said memory has either been read from or written into, wherein said means for generating said data ready signal comprises 1. means, responsive to said request, for generating an acknowledge signal after a first predetermined time period; 2. means, responsive to said acknowledge signal, for commencing the running of the access time of said memory, and 3. means, responsive to the completion of said access time, for providing said data ready signal; C. means, responsive to said data ready signal, for processing the information stored at said location addressed by said processor; and D. means for terminating said memory cycLe after said processing of said information stored at said location addressed by said processor.

Claim 3

means, responsive to said acknowledge signal, for commencing the running of the access time of said memory, and

Claim 4

means, responsive to said acknowledge signal, for commencing the running of the access time of said memory, and

Claim 5

The logic of claim 1 further comprising: A. means, responsive to said acknowledge signal, for generating a clock signal before the generation of said data ready signal; and B. means, responsive to said clock signal, for initiating conditions preparatory to reading information from or writing information into said memory.

Claim 6

The logic of claim 2 further comprising: A. means for storing a first address; B. means for comparing said first address with said address provided by said processor; and C. means for terminating the operation of said logic when said first address and said address provided by said processor are similar.

Claim 7

means, responsive to the completion of said access time, for providing said data ready signal; C. means, responsive to said data ready signal, for processing the information stored at said location addressed by said processor; and D. means for terminating said memory cycLe after said processing of said information stored at said location addressed by said processor.

Claim 8

means, responsive to the completion of said access time, for providing said data ready signal; C. means, responsive to said data ready signal, for processing the information stored at said location addressed by said processor; and D. means for terminating said memory cycLe after said processing of said information stored at said location addressed by said processor.

Claim 9

The logic of claim 3 further comprising means for enabling said means for comparing between the time said acknowledge signal is generated and the time said clock signal is generated.

Claim 10

The logic of claim 2 further comprising: A. a memory data register coupled with said memory for transferring information into or out of the addressed location of said memory; B. means, responsive to said clock signal, for clearing the contents of said memory data register preparatory to the reading of information out of said memory into said memory data register; and C. means, responsive to said clock signal, for entering information into said memory data register preparatory to the writing of said entered information into said memory from said memory data register.

Claim 11

The logic of claim 5 wherein said means for processing comprises: A. means for determining the type of information stored at said location addressed by said processor; B. means for providing a time interval for executing the instruction included in said information, said time interval dependent upon the type of said information; and C. means for generating a first signal upon the termination of said time interval.

Claim 12

The logic of claim 6 further comprising: A. means for determining that the next instruction to be executed by said processor does not require access with said memory; and B. means responsive to said first signal, for executing said next instruction.

Claim 13

Timing and control logic for coupling a data processor and a memory, said logic comprising: A. means for generating a first signal when said processor has a valid address for addressing a location in said memory; B. means, responsive to said first signal, for generating a second signal; C. means, responsive to said second signal, for initiating conditions preparatory to reading of information from said addressed location of said memory; D. means, coupled to receive a third signal from said memory, for indicating that said memory has read said information from said addressed location, said third signal being generated by said memory after a time interval solely dependent upon the access time of said memory; E. means, responsive to said third signal, for operating upon said information read from said addressed location; and F. means for terminating said coupling provided by said logic after a predetermined time period from the generation of said first signal.

Claim 14

Timing and control logic for coupling a data processor and a memory, said logic comprising: A. means for generating a first signal when said processor has a valid address for addressing a location in said memory; B. means, responsive to said first signal, for generating a second signal; C. means, responsive to said second signal, for initiating conditions preparatory to reading of information from said addressed location of said memory; D. means, coupled to receive a third signal from said memory, for indicating that said memory has read said information from said addressed location, said third signal being generated by said memory after a time interval solely dependent upon the access time of said memory; E. means, responsive to said third signal, for operating upon said information read from said addressed location; and F. means for terminating said coupling provided by said logic after a predetermined time period from the generation of said first signal.

Claim 15

Timing and control logic for coupling a data processor with a first memory and a second memory, said first memory having a first access time and a first cycle time, and said second memory having a second access time and a second cycle time, said logic comprising: A. means for addressing either said first or said second memory; B. means for generating a cycle request signal when either said first or said second memory is addressed by said means for addressing; C. means, responsive to said cycle request signal, for generating a first signal; D. means, responsive to said first signal, for initiating conditions of the addressed memory preparatory to reading or writing information with said addressed memory; E. means for generating a data ready signal after the expiration of either said first access time or said second access time dependent upon which of said memories is addressed, said data ready signal indicating that information has either been read from or written into said memory; F. means, responsive to said data ready signal, for executing said information read from said addressed memory; and G. means for terminating said coupling provided by said logic after the expiration of either said first cycle time or said second cycle time dependent upon which of said memories is addressed.

Claim 16

Timing and control logic for coupling a data processor with a first memory and a second memory, said first memory having a first access time and a first cycle time, and said second memory having a second access time and a second cycle time, said logic comprising: A. means for addressing either said first or said second memory; B. means for generating a cycle request signal when either said first or said second memory is addressed by said means for addressing; C. means, responsive to said cycle request signal, for generating a first signal; D. means, responsive to said first signal, for initiating conditions of the addressed memory preparatory to reading or writing information with said addressed memory; E. means for generating a data ready signal after the expiration of either said first access time or said second access time dependent upon which of said memories is addressed, said data ready signal indicating that information has either been read from or written into said memory; F. means, responsive to said data ready signal, for executing said information read from said addressed memory; and G. means for terminating said coupling provided by said logic after the expiration of either said first cycle time or said second cycle time dependent upon which of said memories is addressed.

Claim 17

The logic of claim 9 further comprising: A. means for storing a first address; B. means for comparing said first address with said address provided by said processor; and C. means for terminating the operation of said logic when said first address and said address provided by said processor are similar.

Claim 18

The logic of claim 9 further comprising: A. a memory data register coupled with said memories for transferring information into or out of the addressed one of said memories; B. means, responsive to said first signal, for clearing the contents of said memory data register preparatory to the reading of information out of said addressed memory into said memory data register; and C. means, responsive to said first signal, for entering information into said memory data register preparatory to the writing of said entered information into said addressed memory from said memory data register.

Claim 19

The logic of claim 9 further comprising: A. means for determining that the next instruction to be executed by said processor does not require access with either of said memories; and B. means for executing said next instruction immediately following the execution of said information read from said addressed memory.

Claim 20

Timing and control logic for coupling a first processor and a second processor with a memory, said logic comprising: A. means for generating a first signal when either said first processor or said second processor has an address for addressing a location in said memory; B. means, responsive to said first signal, for generating a second signal; C. means, responsive to said second signal, for initiating conditions preparatiory to reading of information from said addressed location of said memory; D. means, coupled to receive a third signal from said memory, for indicating that said memory has read said information from said addressed location, said third signal being generated by said memory after a time interval solely dependent upon the access time of said memory; E. means, responsive to said third signal, for operating upon said information read from said addressed location; and F. means for terminating said coupling provided by said logic after a predetermined time period from the generation of said first signal.

Claim 21

Timing and control logic for coupling a first processor and a second processor with a memory, said logic comprising: A. means for generating a first signal when either said first processor or said second processor has an address for addressing a location in said memory; B. means, responsive to said first signal, for generating a second signal; C. means, responsive to said second signal, for initiating conditions preparatiory to reading of information from said addressed location of said memory; D. means, coupled to receive a third signal from said memory, for indicating that said memory has read said information from said addressed location, said third signal being generated by said memory after a time interval solely dependent upon the access time of said memory; E. means, responsive to said third signal, for operating upon said information read from said addressed location; and F. means for terminating said coupling provided by said logic after a predetermined time period from the generation of said first signal.

Claim 22

The logic of claim 13 further comprising: A. first means for acknowledging the generation of said first signal; B. second means for acknowledging the generation of said first signal; and C. priority control means for enabling one of said processors to have access to said memory, said priority control means having means for inhibiting the acknowledgment of either said first or second means for acknowledging dependent upon which of said processors is enabled for access to said memory.

Claim 23

Timing and control logic for coupling either of first and second processors with either of first and second memories, said first memory having a first access time and a first cycle time, and said second memory having a second access time and a second cycle time, said logic comprising: A. priority control means for enabling one of said processors; B. means for addressing either said first or said second memory; C. means for providing an address to said means for addressing from said enabled one of said processors; D. means for generating a cycle request signal when either said first or said second memory is addressed by said means for addressing; E. means, responsive to said cycle request signal, for generating a first signal; F. means, responsive to said first signal, for initiating conditions of the addressed memory preparatory to reading or writing information with said addressed memory; G. means for generating a data ready signal after the expiration of either said first access time or said second access time dependent upon which of said memories is addressed, said data ready signal indicating that information has either been read from or written into said memory; H. means, responsive to said data ready signal, for executing said information read from said addressed memory; and I. means for terminating said coupling provided by said logic after the expiration of either said first cycle time or said second cycle time dependent upon which of said memories is addressed.

Claim 24

Timing and control logic for coupling either of first and second processors with either of first and second memories, said first memory having a first access time and a first cycle time, and said second memory having a second access time and a second cycle time, said logic comprising: A. priority control means for enabling one of said processors; B. means for addressing either said first or said second memory; C. means for providing an address to said means for addressing from said enabled one of said processors; D. means for generating a cycle request signal when either said first or said second memory is addressed by said means for addressing; E. means, responsive to said cycle request signal, for generating a first signal; F. means, responsive to said first signal, for initiating conditions of the addressed memory preparatory to reading or writing information with said addressed memory; G. means for generating a data ready signal after the expiration of either said first access time or said second access time dependent upon which of said memories is addressed, said data ready signal indicating that information has either been read from or written into said memory; H. means, responsive to said data ready signal, for executing said information read from said addressed memory; and I. means for terminating said coupling provided by said logic after the expiration of either said first cycle time or said second cycle time dependent upon which of said memories is addressed.