Patent US3746973A successfully refreshed from Google Patents.
US3746973A
Expired / Lapsed
US
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Testing of metallization networks on insulative substrates supporting semiconductor chips
Assignee: International Business Machines Corp
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Filing: 1972-05-05
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Granted: 1973-07-17
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Expires: 1992-05-05
Abstract
Abstract A method for testing the interconnector network on insulative substrates on which integrated circuit chips are to be mounted. The method involves testing for the operability of said interconnector network prior to the mounting of the chips by temporarily mounting at the chip sites a plurality of test chips. Each of these test chips contains a plurality of diodes which respectively connect the chip terminals to a common terminal. The chip terminals are connected to the interconnector network and the common terminal is externally accessible through the substrate. Potential levels are selectively applied to a plurality of test points in the network and differences in potential level between these test points and/or between the points and one or more of the common terminals are determined.
Inventors
- 👤 Mahon M Mc
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 05:26
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2886
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
137 words
In the fabrication of integrated circuit packages wherein a plurality of semiconductor integrated circuit chips are mounted at a plurality of chip sites on an insulative substrate having a network of conductive interconnectors for interconnecting terminals of said plurality of chips, a method of testing said conductive interconnector network prior to the mounting of said chips which comprises temporarily mounting at a plurality of said chip sites, a plurality of semiconductor test chips, each of said test chips having a plurality of unidirectional semiconductor devices, each device respectively connecting a terminal of said chip to a common terminal, applying selected potential levels to a plurality of test points in the conductive interconnector network connected to said teSt chip terminals, and determining differences in potential levels respectively between said points and/or between said points and said common terminals.
Claim 2
Dependent Claim
137 words
In the fabrication of integrated circuit packages wherein a plurality of semiconductor integrated circuit chips are mounted at a plurality of chip sites on an insulative substrate having a network of conductive interconnectors for interconnecting terminals of said plurality of chips, a method of testing said conductive interconnector network prior to the mounting of said chips which comprises temporarily mounting at a plurality of said chip sites, a plurality of semiconductor test chips, each of said test chips having a plurality of unidirectional semiconductor devices, each device respectively connecting a terminal of said chip to a common terminal, applying selected potential levels to a plurality of test points in the conductive interconnector network connected to said teSt chip terminals, and determining differences in potential levels respectively between said points and/or between said points and said common terminals.
Claim 3
Dependent Claim
12 words
The testing method of claim 1 wherein said unidirectional devices are diodes.
Claim 4
Dependent Claim
43 words
The testing method of claim 1 wherein said chips are temporarily mounted by fusible metal contacts between terminals on said chip and corresponding interconnector network terminals, and upon completion of testing, said temporary chips are removed from said substrate by fusing said contacts.
Claim 5
Dependent Claim
40 words
The testing method of claim 1 wherein the group of test points respectively associated with each of the chips and connected to the terminals of said chip are arranged spaced from said chip around the periphery of the chip site.
Claim 6
Dependent Claim
40 words
The method of claim 4 wherein said groups of test points are contacted with test probes one group at a time, said test probes applying said selective potential levels to at least one of the test points in said groups.
Claim 7
Dependent Claim
43 words
The method of claim 5 wherein the connections between the groups of test points associated with a respective chip and the terminals of said chip are tested by determining differences in potential levels between points in said groups contacted by said test probes.
Claim 8
Dependent Claim
60 words
The method of claim 5 wherein network interconnections between terminals of different chips mounted on said substrate are tested by applying a potential level to the test point associated with the terminal in the chip being probed which is being connected with a terminal in another chip, and sensing the potential level at the common terminal in said other chip.
References Cited (Backward Citations)
US1977703A
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US3405361A
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US3192307A
Cited
US3560907A
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US3609538A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-16 | 1977-01-15 | 1977-07-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-16 | 1981-01-15 | 1981-07-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-16 | 1985-01-15 | 1985-07-17 | $7700.00 | Window Closed / Lapsed |