Slow rotational speed alarm

Claim 2

In a machine having a shaft, an alarm for indicating that said shaft is moving at less than at a preselected speed, said alarm comprising means for generating input pulses at a frequency proportional to the speed of the shaft, means for generating a reference signal of predetermined duration relative to said preselected speed, signalling means having a normal and a signalling condition, means comparing the reference signal duration with the input signal interval for actuating said signalling means to give a signalling condition only when the input pulse interval is greater than the duration of said reference signal, said last-named means comprising a set-reset memory circuit that produces an output signal at one binary logic state when set and an output signal at the complement binary logic state when reset, a gating circuit having an output determineD by an input and the output signal of said memory circuit, the output state of said gating circuit determining the condition of said signalling means,and means for providing a set input to said memory circuit at the end of said predetermined duration of the reference signal.

Claim 3

In a machine according to claim 1, said means for generating a reference signal comprising a monostable multivibrator that is triggered by an input pulse.

Claim 4

In a machine according to claim 1, said means for actuating said signalling means further comprising set-reset latch circuitry for latching said signalling means in the condition to which the signalling means is driven, said latch circuitry including said gating circuit.

Claim 5

In a machine according to claim 1, said machine being a combine and said shaft being a power driven shaft thereon.

Claim 6

An alarm for indicating that the output of a function is less than at a preselected amount, said alarm comprising means for generating input pulses at a frequency proportional to the analog function, a monostable multivibrator for generating a reference signal of predetermined duration relative to said preselected magnitude of said analog function, said multivibrator being triggered by an input pulse, signalling means, and means for actuating said signalling means to produce a signalling condition when the input pulse interval is greater than the duration of said reference signal; said last-named means comprising a set-reset memory circuit having an output at one binary logic state when set and an output at the complement binary logic state when reset, means responsive to the input pulse following the pulse that triggers the multivibrator for providing a reset pulse for said memory circuit, and means comprising an input to said memory circuit from the output of said multivibrator for providing a set pulse for said memory circuit at the end of the multivibrator interval that cancels the effect of said reset pulse when the input pulse frequency is less than the duration of said reference signal.

Claim 7

An alarm for indicating that the output of a function is less than at a preselected amount, said alarm comprising means for generating input pulses at a frequency proportional to the analog function, a monostable multivibrator for generating a reference signal of predetermined duration relative to said preselected magnitude of said analog function, said multivibrator being triggered by an input pulse, signalling means, and means for actuating said signalling means to produce a signalling condition when the input pulse interval is greater than the duration of said reference signal; said last-named means comprising a set-reset memory circuit having an output at one binary logic state when set and an output at the complement binary logic state when reset, means responsive to the input pulse following the pulse that triggers the multivibrator for providing a reset pulse for said memory circuit, and means comprising an input to said memory circuit from the output of said multivibrator for providing a set pulse for said memory circuit at the end of the multivibrator interval that cancels the effect of said reset pulse when the input pulse frequency is less than the duration of said reference signal.

Claim 8

An alarm according to claim 5 in which the set pulse is derived by a differentiation of the reference signal and the reset pulse is derived by a differentiation of the input pulses, the reset pulse having a shorter time constant than that of the set pulse.

Claim 9

An alarm according to claim 5 including adjusting means for varying the duration of said reference signal.

Claim 10

An alarm according to claim 5 including a set-reset latch circuit forming part of said actuating means for latching said signalling means in a signalling condition or in non-signalling condition when driven thereto; said latch circuit including a transistor that constitutes a switch for said signalling means, and a logic gate, the transistor having a collector connected to an input of the logic gate and the logic gate having an output connected to the base of the transistor.

Claim 11

An alarm according to claim 5 including means for increasing the duration of the reference signal when the signalling device is on compared to the duration of said reference signal when the signalling device is off.

Claim 12

Circuitry having signalling means and means for actuating the signalling means, said actuating means including a flip-flop having set and reset inputs and an output, said output being at one binary logic state when triggered by a pulse at the set input and being at the complement state when triggered by a pulse at the reset input, means for generating input pulses to said reset input, and circuit means including a monostable multivibrator triggered by a signal at the reset input, said multivibrator producing an output signal of predetermined duration, said circuit means applying set pulses to said set input through the output of said multivibrator, the reset pulses preventing setting of said flip-flop if received from said generating means at intervals greater than the duration of said multivibrator signal, said set pulse being of such magnitude and duration as to cancel the effect of a reSet pulse if an input pulse is received at said reset input after the duration of said multivibrator signal.

Claim 13

Circuitry having signalling means and means for actuating the signalling means, said actuating means including a flip-flop having set and reset inputs and an output, said output being at one binary logic state when triggered by a pulse at the set input and being at the complement state when triggered by a pulse at the reset input, means for generating input pulses to said reset input, and circuit means including a monostable multivibrator triggered by a signal at the reset input, said multivibrator producing an output signal of predetermined duration, said circuit means applying set pulses to said set input through the output of said multivibrator, the reset pulses preventing setting of said flip-flop if received from said generating means at intervals greater than the duration of said multivibrator signal, said set pulse being of such magnitude and duration as to cancel the effect of a reSet pulse if an input pulse is received at said reset input after the duration of said multivibrator signal.