US3639911A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital processor having automatic conflict-resolving logic
Assignee: Incoterm Corp
•
Filing: 1970-06-10
•
Granted: 1972-02-01
•
Expires: 1990-06-10
Abstract
Abstract A digital data processor for transferring information with associated devices has an automatically operating executive, i.e. conflict-resolving, logic unit that resolves operating conflicts arising from the asynchronous operations of the processor and the associated devices when one calls for an information transfer with the other. The processor operates under control of the logic unit to store off interrupted status at and load in new status information from memory locations dedicated to this purpose and identified, at least in part, by the particular device with which the processor is operating.
Inventors
- 👤 Neil G Frieband
- 👤 Douglas O Kendrick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 00:41
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812
Claims Analysis
Total Claims: 41
Claim 1
Independent Claim
394 words
A digital data processor for fetching and executing stored program instructions, some of which call for a transfer of digital information with any specified one of plural data processing devices capable of operation asynchronously of the processor, and having status components that store information identifying the operative status of the processor and an addressable memory element, said processor further having the improvement comprising A. logic gate means for determining the presence of an interrupt-request signal from an identified one of said devices, and for determining the absence of a device-ready signal from an identified one of said devices, B. logic switch means 1. normally operative in a first state for maintaining said processor in an instruction-executing state for the execution of programmed instructions, and 2. responsive to any one of said determinations from said gate means for switching from said first state to a second state for maintaining said processor in an executive state for transferring operation from one sequence of instructions to another, and C. sequence control means 1. connected with said gate means and with said switch means, 2. rendered in a first condition when said switch means is in saId first state and in a second condition when said switch means is in said second state, 3. responsive to an interrupt determination by said gate means to assume said second condition and successively a. write the contents of said processor status components into said memory element at a first location the address of which is associated with said identified device, b. read previously stored status information from said memory element at a second location the address of which is associated with said identified device and load it into said processor status components, c. condition said switch means to switch from said second state to said first state, and 4. responsive to a device-ready absence determination by said gate means to assume said second condition and successively a. write the contents of said processor status components into said memory element at a second location the address of which is associated with said identified device, b. read previously stored status information from said memory element at a first location the address of which is associated with said identified device and load it into said processor status components, and c. condition said switch means to switch from said second state to said first state.
Claim 2
Dependent Claim
394 words
A digital data processor for fetching and executing stored program instructions, some of which call for a transfer of digital information with any specified one of plural data processing devices capable of operation asynchronously of the processor, and having status components that store information identifying the operative status of the processor and an addressable memory element, said processor further having the improvement comprising A. logic gate means for determining the presence of an interrupt-request signal from an identified one of said devices, and for determining the absence of a device-ready signal from an identified one of said devices, B. logic switch means 1. normally operative in a first state for maintaining said processor in an instruction-executing state for the execution of programmed instructions, and 2. responsive to any one of said determinations from said gate means for switching from said first state to a second state for maintaining said processor in an executive state for transferring operation from one sequence of instructions to another, and C. sequence control means 1. connected with said gate means and with said switch means, 2. rendered in a first condition when said switch means is in saId first state and in a second condition when said switch means is in said second state, 3. responsive to an interrupt determination by said gate means to assume said second condition and successively a. write the contents of said processor status components into said memory element at a first location the address of which is associated with said identified device, b. read previously stored status information from said memory element at a second location the address of which is associated with said identified device and load it into said processor status components, c. condition said switch means to switch from said second state to said first state, and 4. responsive to a device-ready absence determination by said gate means to assume said second condition and successively a. write the contents of said processor status components into said memory element at a second location the address of which is associated with said identified device, b. read previously stored status information from said memory element at a first location the address of which is associated with said identified device and load it into said processor status components, and c. condition said switch means to switch from said second state to said first state.
Claim 3
Dependent Claim
44 words
responsive to any one of said determinations from said gate means for switching from said first state to a second state for maintaining said processor in an executive state for transferring operation from one sequence of instructions to another, and C. sequence control means
Claim 4
Dependent Claim
44 words
responsive to any one of said determinations from said gate means for switching from said first state to a second state for maintaining said processor in an executive state for transferring operation from one sequence of instructions to another, and C. sequence control means
Claim 5
Dependent Claim
28 words
rendered in a first condition when said switch means is in saId first state and in a second condition when said switch means is in said second state,
Claim 6
Dependent Claim
28 words
rendered in a first condition when said switch means is in saId first state and in a second condition when said switch means is in said second state,
Claim 7
Dependent Claim
41 words
responsive to said determination from said gate means for switching from said first state to a second state for maintaining said processor in an executive state for transferring operation from one sequence of instructions to another, and C. sequence control means
Claim 8
Dependent Claim
41 words
responsive to said determination from said gate means for switching from said first state to a second state for maintaining said processor in an executive state for transferring operation from one sequence of instructions to another, and C. sequence control means
Claim 9
Dependent Claim
28 words
rendered in a first condition when said switch means is in said first state and in a second condition when said switch means is in said second state,
Claim 10
Dependent Claim
28 words
rendered in a first condition when said switch means is in said first state and in a second condition when said switch means is in said second state,
Claim 11
Dependent Claim
26 words
A processor as defined in claim 1 in which said status components include program counter means, arithmetic condition status register means, and accumulator status register means.
Claim 12
Dependent Claim
41 words
responsive to said determination from said gate means for switching from said first state to a second state for maintaining said processor in an executive state for transferring operation from one sequence of instructions to another, and C. sequence control means
Claim 13
Dependent Claim
41 words
responsive to said determination from said gate means for switching from said first state to a second state for maintaining said processor in an executive state for transferring operation from one sequence of instructions to another, and C. sequence control means
Claim 14
Dependent Claim
28 words
rendered in a first condition when said switch means is in said first state and in a second condition when said switch means is in said second state,
Claim 15
Dependent Claim
28 words
rendered in a first condition when said switch means is in said first state and in a second condition when said switch means is in said second state,
Claim 16
Dependent Claim
92 words
responsive to said device-ready absence determination by said gate means to assume said second condition and successively a. write the contents of said processor status components into said memory element at a second location the address of which is associated with said identified device, b. read previously stored status information from said memory element at a first location the address of which is associated with said identified device and load it into said processor status components, and c. condition said switch means to switch from said second state to said first state.
Claim 17
Dependent Claim
92 words
responsive to said device-ready absence determination by said gate means to assume said second condition and successively a. write the contents of said processor status components into said memory element at a second location the address of which is associated with said identified device, b. read previously stored status information from said memory element at a first location the address of which is associated with said identified device and load it into said processor status components, and c. condition said switch means to switch from said second state to said first state.
Claim 18
Dependent Claim
39 words
A processor as defined in claim 1 further including address signal producing means producing said first and said second memory addresses associated with each said device in response to said determination from said gate means and the device identification.
Claim 19
Dependent Claim
90 words
responsive to said interrupt determination by said gate means to assume said second condition and successively a. write the contents of said processor status components into said memory element at a first location the address of which is associated with said identified device, b. read previously stored status information from said memory element at a second location the address which is associated with said identified device and load it into said processor status components, and c. condition said switch means to switch from said second state to said first state.
Claim 20
Dependent Claim
90 words
responsive to said interrupt determination by said gate means to assume said second condition and successively a. write the contents of said processor status components into said memory element at a first location the address of which is associated with said identified device, b. read previously stored status information from said memory element at a second location the address which is associated with said identified device and load it into said processor status components, and c. condition said switch means to switch from said second state to said first state.
Claim 21
Dependent Claim
91 words
responsive to an interrupt determination by said gate means to assume said second condition and successively a. write the contents of said processor status components into said memory element at a first location the address of which is associated with said identified device, b. read previously stored status information from said memory element at a second location the address of which is associated with said identified device and load it into said processor status components, c. condition said switch means to switch from said second state to said first state, and
Claim 22
Dependent Claim
91 words
responsive to an interrupt determination by said gate means to assume said second condition and successively a. write the contents of said processor status components into said memory element at a first location the address of which is associated with said identified device, b. read previously stored status information from said memory element at a second location the address of which is associated with said identified device and load it into said processor status components, c. condition said switch means to switch from said second state to said first state, and
Claim 23
Dependent Claim
92 words
responsive to a device-ready absence determination by said gate means to assume said second condition and successively a. write the contents of said processor status components into said memory element at a second location the address of which is associated with said identified device, b. read previously stored status information from said memory element at a first location the address of which is associated with said identified device and load it into said processor status components, and c. condition said switch means to switch from said second state to said first state.
Claim 24
Dependent Claim
92 words
responsive to a device-ready absence determination by said gate means to assume said second condition and successively a. write the contents of said processor status components into said memory element at a second location the address of which is associated with said identified device, b. read previously stored status information from said memory element at a first location the address of which is associated with said identified device and load it into said processor status components, and c. condition said switch means to switch from said second state to said first state.
Claim 25
Dependent Claim
65 words
A processor as defined in claim 3 A. in which at least some of said data processing devices are organized in a first group, and B. in which said sequence control means includes logic elements for operating said address means to produce a memory address identifying the same first memory location in response to an interrupt determination from any device in said first group thereof.
Claim 26
Dependent Claim
49 words
A processor as defined in claim 4 in which said logic elements of said sequence control means operates said address signal producing means to produce a memory address identifying a different second memory location in response to a device-ready absence determination from any device in said first group thereof.
Claim 27
Dependent Claim
36 words
A processor as defined in claim 5 in which said sequence control means includes further logic elements for inhibiting said devices from raising new interrupt request signals during the execution of information transfers with said devices.
Claim 28
Dependent Claim
52 words
A processor as defined in claim 5 in which said further logic elements of said sequence control means enable said devices to send new interrupt-request signals to said processor only upon the completion of an instruction and upon the completion of an operation with said logic switch means in said second state.
Claim 29
Dependent Claim
40 words
A processor as defined in claim 1 further comprising logic elements for maintaining said logic switch means in said first state during an information-transferring operation with one of said devices in response to a device ready-indicating signal from said device.
Claim 30
Dependent Claim
52 words
A processor as defined in claim 1 A. which further operates to signal an identified device for a signal-transferring operation therewith, and B. further including gate means maintaining said logic switch means in said first state in response to a timely ready-indicating signal from said identified device signaled for said transferring operation.
Claim 31
Dependent Claim
53 words
A processor as defined in claim 1 in which said logic gate means includes logic elements for determining the absence of a device ready signal in response to the coincidence of an instruction calling for a signal transfer with one said device and the absence of a timely ready signal from said device.
Claim 32
Dependent Claim
50 words
A processor as defined in claim 1 in which said logic switch Means includes logic elements for determining the presence of an interrupt-request signal in response to the coincidence of the completion of the execution of an instruction and the presence of an interrupt request signal from one said device.
Claim 33
Dependent Claim
86 words
A digital data processor for fetching and executing stored program instructions, some of which call for a transfer of digital information with any specified one of plural data processing devices capable of operation asynchronously of the processor, and having status components that store information identifying the operative status of the processor and an addressable memory element, said processor further having the improvement comprising A. logic gate means for determining the presence of an interrupt-request signal from an identified one of said devices, B. logic switch means
Claim 34
Dependent Claim
86 words
A digital data processor for fetching and executing stored program instructions, some of which call for a transfer of digital information with any specified one of plural data processing devices capable of operation asynchronously of the processor, and having status components that store information identifying the operative status of the processor and an addressable memory element, said processor further having the improvement comprising A. logic gate means for determining the presence of an interrupt-request signal from an identified one of said devices, B. logic switch means
Claim 35
Dependent Claim
86 words
A digital data processor for fetching and executing stored program instructions, some of which call for a transfer of digital information with any specified one of plural data processing devices capable of operation asynchronously of the processor, and having status components that store information identifying the operative status of the processor and an addressable memory element, said processor further having the improvement comprising A. logic gate means for determining the absence of a device-ready signal from an identified one of said devices, B. logic switch means
Claim 36
Dependent Claim
86 words
A digital data processor for fetching and executing stored program instructions, some of which call for a transfer of digital information with any specified one of plural data processing devices capable of operation asynchronously of the processor, and having status components that store information identifying the operative status of the processor and an addressable memory element, said processor further having the improvement comprising A. logic gate means for determining the absence of a device-ready signal from an identified one of said devices, B. logic switch means
Claim 37
Dependent Claim
207 words
SequencinG and gating means for providing automatic executive operation in a stored-program, digital data processor operating with devices that operate at least partially asynchronously of the processor, the processor having components that contain the operative status of the processor and having a memory element, said sequencing and gating means comprising A. conflict-determining first gate means for determining the occurrence and identity of a conflict condition for said processor in connection with the operation thereof, with at least one of said devices, B. processor-state register means operating in a first state for conditioning said processor to fetch and execute instructions and operating in a second state for conditioning said processor for said automatic executive operation, and assuming said second state when it receives signals responsive to conflict determinations from said first gate means, and C. information-transferring second gate means responsive to a conflict determination from said first gate means to produce automatically a sequence of gating signals for first storing the contents of said processor status components in locations in said memory element which are associated with the identity of the determined conflict condition and loading new information into said processor status components from further locations in said memory element which are associated with said determined conflict condition.
Claim 38
Dependent Claim
207 words
SequencinG and gating means for providing automatic executive operation in a stored-program, digital data processor operating with devices that operate at least partially asynchronously of the processor, the processor having components that contain the operative status of the processor and having a memory element, said sequencing and gating means comprising A. conflict-determining first gate means for determining the occurrence and identity of a conflict condition for said processor in connection with the operation thereof, with at least one of said devices, B. processor-state register means operating in a first state for conditioning said processor to fetch and execute instructions and operating in a second state for conditioning said processor for said automatic executive operation, and assuming said second state when it receives signals responsive to conflict determinations from said first gate means, and C. information-transferring second gate means responsive to a conflict determination from said first gate means to produce automatically a sequence of gating signals for first storing the contents of said processor status components in locations in said memory element which are associated with the identity of the determined conflict condition and loading new information into said processor status components from further locations in said memory element which are associated with said determined conflict condition.
Claim 39
Dependent Claim
164 words
Sequencing and gating means as defined in claim 14 A. in which said first gating means identifies one of at least two conflict conditions with any identified one of said devices, B. further including memory address generating means for producing the address of either of two memory locations assigned to each such device, and C. in which said second gating means and address generating means include logic elements for responding to said determination of a first of said conflict conditions to first produce said first memory address associated with the identified device for storing at said address the contents of said processor status components and then to produce the second of said addresses for said identified device for reading therefrom said new information for said processor status components, and for responding to said determination of the second of said conflict situations to first produce said second address associated with the identified device and then to produce said first address associated with said identified device.
Claim 40
Dependent Claim
99 words
Sequencing and gating means as defined in claim 14 A. further including memory address generating means for producing the address of either of first and second memory locations assigned to each such device, and B. in which said second gating means and said address generating means include logic elements for producing said first memory address identically for the determination of a conflict condition with any one of a group of said devices and for producing said second memory address differently in response to the determination of a conflict condition with any one of said devices in said group thereof.
Claim 41
Dependent Claim
37 words
Sequencing and gating means as defined in claim 16 in which further logic elements render said first gating means responsive to a device-interrupting conflict condition only during the execution of instructions read from a first memory address.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-01-31 | 1975-08-02 | 1976-02-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-01-31 | 1979-08-02 | 1980-02-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-01-31 | 1983-08-02 | 1984-02-01 | $7700.00 | Window Closed / Lapsed |